Apparatus having selectively-activated termination circuitry

An apparatus, comprising:

• a first plurality of signal lines;
• a second plurality of signal lines;
• a controller connected to the first plurality of signal lines and connected to the second plurality of signal lines;
• a first die connected to the first plurality of signal lines and connected to the second plurality of signal lines, wherein the first die comprises first termination circuitry connected to a particular signal line of the second plurality of signal lines, and wherein the first termination circuitry comprises a first plurality of pull-up devices and a first plurality of pull-down devices;
• and
• a second die connected to the first plurality of signal lines and connected to the second plurality of signal lines, wherein the second die comprises second termination circuitry connected to the particular signal line, and wherein the second termination circuitry comprises a second plurality of pull-up devices and a second plurality of pull-down devices;
• wherein the first die is configured to activate a first pattern of pull-up devices and pull-down devices of the first plurality of pull-up devices and the first plurality of pull-down devices in response to receiving a particular combination of signal values on the first plurality of signal lines;
• and
• wherein the second die is configured to activate a second pattern, different than the first pattern, of pull-up devices and pull-down devices of the second plurality of pull-up devices and the second plurality of pull-down devices in response to receiving the particular combination of signal values on the first plurality of signal lines.

A memory system, comprising:

• a first memory device comprising a first plurality of die;
• a second memory device comprising a second plurality of die;
• a controller;
• an address bus comprising a first plurality of signal lines connected to the first memory device, connected to the second memory device, and connected to the controller;
• and
• a data bus comprising a second plurality of signal lines connected to the first memory device, connected to the second memory device, and connected to the controller;
• wherein each die of the first plurality of die comprises respective termination circuitry connected to a particular signal line of the second plurality of signal lines and configured to adjust an input impedance of the respective particular signal line;
• wherein each die of the second plurality of die comprises respective termination circuitry connected to the particular signal line;
• wherein the first memory device is configured to activate the respective termination circuitry of at least one die of the first plurality of die in response to receiving a particular combination of signal values on the first plurality of signal lines;
• and
• wherein the second memory device is configured to deactivate the respective termination circuitry of at least one die of the second plurality of die in response to receiving the particular combination of signal values on the first plurality of signal lines.