Method and non-transitory computer-readable storage medium and apparatus for decoding low-density parity-check (LDPC) code

A non-transitory computer-readable storage medium having stored therein program code that, when loaded and executed by a processing unit in a Low-Density Parity-Check (LDPC) decoder, causes the processing unit to:

• determine whether a bit flipping algorithm when decoding a codeword enters a trapping state after an observation period during which a sequential selection strategy is used, wherein the codeword is divided into a plurality of chunks in fixed-length and the sequential selection strategy indicates sequentially selecting the chunks in the codeword, and a total number of bits in each chunk is a multiple of 16;
• and
• modify a scheduling strategy to a non-sequential selection strategy and perform the bit flipping algorithm on the codeword under the non-sequential selection strategy when the bit flipping algorithm enters the trapping state, wherein the non-sequential selection strategy indicates an arbitrary selection combination of the chunks in the codeword for the bit flipping algorithm which is different from that under the sequential selection strategy,
• wherein the bit flipping algorithm is performed on one selected chunk only each time under each of the sequential selection strategy and the non-sequential selection strategy for changing states of one or more hard bits or variable nodes that are determined to be faulty in the selected chunk according to syndromes, hard bits or variable nodes, and soft bits corresponding to hard bits or variable nodes.

An apparatus for decoding a Low-Density Parity-Check (LDPC) code, comprising:

• a variable-node calculation circuitry;
• and
• a processing unit, coupled to the variable-node calculation circuitry, arranged operably to:
• determine whether a bit flipping algorithm when decoding a codeword enters a trapping state after an observation period during which a sequential selection strategy is used, wherein the codeword is divided into a plurality of chunks in fixed-length and the sequential selection strategy indicates sequentially selecting the chunks in the codeword, and a total number of bits in each chunk is a multiple of 16;
• and modify a scheduling strategy to a non-sequential selection strategy and drive the variable-node calculation circuitry to perform the bit flipping algorithm on the codeword under the non-sequential selection strategy when the bit flipping algorithm enters the trapping state, wherein the non-sequential selection strategy indicates an arbitrary selection combination of the chunks in the codeword for the bit flipping algorithm, which is different from that under the sequential selection strategy,
• wherein the bit flipping algorithm is performed on one selected chunk only each time under each of the sequential selection strategy and the non-sequential selection strategy for changing states of one or more hard bits or variable nodes that are determined to be faulty in the selected chunk according to syndromes, hard bits or variable nodes, and soft bits corresponding to hard bits or variable nodes.