Analog-to-digital converter (ADC) with reference ADC path receiving attenuated input to generate error codes for second and third harmonics by counting negative and positive codes

A nonlinear-error-corrected Analog-to-Digital Converter (ADC) comprising:

• an analog front end receiving an analog input;
• an attenuator in the analog front end for attenuating the analog input to generate an attenuated analog input;
• a data channel receiving the analog input and a channel sampling clock;
• a reference channel receiving the attenuated analog input and the channel sampling clock also received by a data channel;
• wherein the data channel and the reference channel each comprises:
• an ADC for converting a sampled analog input into a digital output for a channel, the digital output having a digital value representing the sampled analog input for the channel;
• an analog switch that samples an analog input in response to a delayed clock;
• a static error corrector for correcting the digital output for offset, gain, and mismatch errors;
• wherein the channel further comprises:
• a nonlinear channel corrector receiving a second coefficient and a third coefficient, and also receiving the digital output for the channel from the static error corrector;
• the nonlinear channel corrector adding a second error term and adding a third error term to the digital output for the channel to generate a corrected digital output for the channel;
• the nonlinear channel corrector generating a normalized code value by dividing the digital output by a range of the digital output;
• the nonlinear channel corrector squaring the normalized code value to get a squared value, and multiplying the squared value by the second coefficient to generate the second error term;
• the nonlinear channel corrector cubing the normalized code value to get a cubed value, and multiplying the cubed value by the third coefficient to generate the third error term;
• a nonlinear detector that receives the corrected digital output for the data channel and generates the second coefficient, the nonlinear detector further comprising:
• a second counter that is incremented by a sign bit of the corrected digital output for the data channel to generate a second count;
• a second cost function calculator that generates a second cost function as a function of the second count and that resets the second counter when the second cost function is calculated;
• and
• a second loop updater that updates the second coefficient by subtracting a sign of the second cost function multiplied by a second stepsize from a prior value of the second coefficient,
• whereby sign bits are counted to generate the second cost function to update the second coefficient for nonlinear error correction.

An Analog-to-Digital Converter (ADC) comprising:

• an analog input;
• a corrected digital output;
• a plurality of channels including a data channel and a reference channel;
• an attenuator that attenuates the analog input to generate an attenuated analog input that is input to the reference channel;
• wherein each channel in the plurality of channels further comprises:
• a channel ADC having a sampled analog input and a digital output;
• a sampling switch between the analog input and the sampled analog input, the sampling switch responsive to a delayed clock;
• a Successive-Approximation-Register (SAR) that stores a delay setting for the channel;
• and
• a delay element adding a variable delay to a channel clock to generate a delayed clock, wherein the variable delay is determined by the delay setting in the SAR;
• an offset corrector for averaging the digital output from the channel ADC to generate an offset-corrected digital output;
• a gain corrector for generating a moving root-mean-square of the offset-corrected digital output and for dividing the offset-corrected digital output by the moving root-mean-square and multiplying by a moving root-mean-square of a first channel in the plurality of channels to generate a static-corrected digital output;
• a channel correlator for correlating the static-corrected digital output from the channel to static-corrected digital outputs from adjacent channels in the plurality of channels to generate a correlation sign bit for the channel;
• and
• a nonlinear channel corrector that adds a second harmonic distortion (HD2) term to the static-corrected digital output for the channel to generate the corrected digital output for the channel, and generates a normalized Y value by dividing the static-corrected digital output by a range of the static-corrected digital output, and generates the HD2 term by squaring the normalized Y value and multiplying by a HD2 coefficient;
• a calibrator, using the correlation sign bit to decide when to add a test bit to the SAR for a channel, and when to remove the test bit from the SAR for the channel, wherein each correlation sign bit is for adding or removing a test bit from a SAR in a different channel in the plurality of channels;
• a HD2 counter that is incremented by a sign bit of the corrected digital output from the nonlinear channel corrector for the data channel, the HD2 counter having a HD2 count value that is reset after M samples, wherein M is a whole number of at least 16384;
• a HD2 cost function calculator that uses the HD2 count value to generate a HD2 cost function;
• and
• a HD2 updater that updates the HD2 coefficient by subtracting a sign of the HD2 cost function multiplied by a HD2 stepsize from a prior value of the HD2 coefficient,
• whereby HD2 errors are detected by counting sign bits of the corrected digital output of the data channel.