Hybrid analog-to-digital converter with inverter-based residue amplifier
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMartin Kinyua, Eric Soenen
Life of this patent
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Abstract
An apparatus and method for analog to digital conversion of analog input signals are disclosed herein. In some embodiments, an analog-to-digital (ADC) may comprise: a first successive approximation register (SAR) circuit comprising a fast SAR (FSAR) circuit and a residue digital-to-analog converter (RDAC) circuit and a residue amplifier circuit, coupled to the RDAC circuit, comprising an amplifier circuit that is configured to amplify a residual signal generated by the RDAC circuit, wherein the amplifier circuit comprises a deadzone control circuit and a first, second and third inverter stages, wherein the third stage is biased to operate in a sub-threshold region.
Claims20
A physical unclonable function (PUF) generator comprising:
- a plurality of PUF cells, wherein each of the plurality of PUF cells comprises a plurality of transistors;
- a plurality of circuits wherein each of the plurality of circuits is coupled to each of the plurality of PUF cells respectively, wherein the plurality of circuits each is configured to monitoring a voltage level on a node on each of the plurality of PUF cells;
- a population count circuit coupled to the plurality of circuits, wherein the population count circuit is configured to determine a first number of PUF cells having flipped logical states from a first logical state to a second logical state;
- and
- an evaluation logic circuit having an input coupled to the population count circuit and an output coupled to the plurality of circuits, wherein the evaluation logic circuit is configured to compare the first number with a predetermined number of PUF cells, wherein a PUF signature is generated when the number of PUF cells that are at the second logical state are equal to or higher than the predetermined number of PUF cells.
A method to configure a physical unclonable function (PUF) generator for generating a PUF signature, the method comprising:
- coupling a plurality of PUF cells to a plurality of circuits, wherein each of the plurality of PUF cells comprises a first transistor and a second transistor;
- charging a plurality of dynamic nodes in the plurality of PUF cells to a plurality of first voltages through each of the plurality of first transistors;
- discharging the plurality of dynamic nodes to a plurality of second voltages through each of the plurality of second transistors;
- monitoring each of the plurality of second voltages using corresponding circuits;
- flipping logical states of the plurality of PUF cells from a first logical state to a second logical state when the second voltage becomes smaller than a third voltage;
- and
- generating a PUF signature when a number of PUF cells having flipped logical states are more than a predetermined number of PUF cells.
A physical unclonable function (PUF) generator comprising:
- a plurality of PUF cells;
- at least one circuit coupled to each of the plurality of PUF cells, wherein the at least one circuit is configured to monitor a voltage level on a node of each of the plurality of PUF cells;
- a population count circuit coupled to the at least one circuit, wherein the population count circuit is configured to determine a first number of PUF cells having flipped logical states from a first logical state to a second logical state;
- and
- an evaluation logic circuit coupled to the population count circuit and the at least one circuit, wherein the evaluation logic circuit is configured to compare the first number with a predetermined number of PUF cells, wherein a PUF signature is generated when the number of PUF cells that are at the second logical state are equal to or higher than the predetermined number of PUF cells.
Dependencies are inferred from the claim text.