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US 12,231,106 B2Granted
Apparatuses and methods for calibrating adjustable impedances of a semiconductor device
OwnerDean Gansinventor
Life of this patent
Estimating the term…
Abstract
Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.
Claims21
An apparatus comprising:
- a memory controller configured to cause a memory to apply new calibration results to programmable termination resistances by performing operations comprising:
- provide a register read command to a register of a memory;
- receive, responsive to the register read command, at least one bit from the register of the memory;
- determine, based on a value of the at least one bit from the register of the memory, availability or unavailability of new calibration results of a calibration operation associated with the programmable termination resistances;
- and
- provide a latch command to the memory when the value of the at least one bit in the register of the memory indicates the availability of the new calibration results, wherein the latch command is configured to cause the memory to apply the new calibration results to the programmable termination resistances.
3 more elements
A system comprising:
- at least one memory controller configured to:
- provide a register read command;
- receive, responsive to the register read command, at least one bit from a register;
- and
- provide a latch command when a value of the at least one bit from the register indicates availability of new calibration results of a calibration operation;
- first and second memory devices comprising programmable termination resistances, the first and second memory devices each configured to:
- receive the register read command;
- provide the at least one bit from the register;
- receive the latch command;
- and
- apply the new calibration results to the programmable termination resistances responsive to the latch command;
- a shared external resistor coupled to a power supply voltage and the first and second memory devices, wherein the shared external resistor is configured to be used to perform the calibration operation;
- and
- a memory bus coupled to the at least one memory controller and the first and second memory devices, wherein the memory bus is configured to:
- transmit the register read command from the at least one controller to the first and second memory devices;
- transmit, via a data line of the memory bus, the at least one bit from the first and second memory devices to the at least one memory controller;
- and
- transmit the latch command from the at least one memory controller to the first and second memory devices.
15 more elements
A method comprising:
- providing, by a memory controller, a register read command to a register of a memory;
- receiving, by the memory controller and responsive to the register read command, a value of at least one bit in the register of the memory;
- determining, based on the value of the at least one bit in the register of the memory, availability or unavailability of new calibration results of a calibration operation associated with programmable termination resistances of the memory;
- and
- providing, by the memory controller, a latch command to the memory when the value of the at least one bit in the register of the memory indicates the availability of the new calibration results, wherein the latch command is configured to cause the memory to apply the new calibration results to the programmable termination resistances.
2 more elements
A method comprising:
- reading, by a memory controller, a bit from a mode register of a memory, wherein the bit represents a calibration flag, and wherein the bit has a first value or a second value different from the first value;
- and
- sending, by the memory controller, a latch command to the memory when the bit representing the calibration flag has the first value, wherein the latch command causes the memory to apply results of a calibration operation.
Dependencies are inferred from the claim text.