Method of fabricating a semiconductor chip having strength adjustment pattern in bonding layer

A method of fabricating a semiconductor chip, comprising:

• forming a first bonding layer on a first wafer substrate, wherein the first bonding layer has a recess;
• forming a semiconductor component layer, a first interconnect structure layer and an alignment mark on a second wafer substrate, wherein the semiconductor component layer comprises a circuit component and the alignment mark keeps from the circuit component in a lateral direction;
• forming a second bonding layer on the first interconnect structure layer;
• bonding the second wafer substrate to the first wafer substrate by contacting the second bonding layer with the first bonding layer and aligning the recess with the alignment mark, wherein a first portion of the second bonding layer overlapping the recess and a second portion of the second bonding layer in contact with the first bonding layer has a same thickness;
• removing the second wafer substrate;
• forming a second interconnect structure layer on the semiconductor component layer, wherein the second interconnect structure layer and the first interconnect structure layer are located at opposite sides of the semiconductor component layer;
• forming a conductor terminal on the second interconnect structure layer;
• and
• performing a singulation process to obtain a semiconductor chip comprising the semiconductor component layer, the first interconnect structure layer, the second interconnect structure layer and the conductor terminal, wherein the recess is separated from the semiconductor chip by the singulation process.

A method of fabricating a semiconductor chip, comprising:

• forming a first bonding layer on a first wafer substrate;
• sequentially forming a semiconductor component layer, a first interconnect structure layer, and a second bonding layer on a second wafer substrate;
• bonding the second wafer substrate to the first wafer substrate by contacting the second bonding layer with the first bonding layer, wherein an air gap is formed extending along a thickness of the first bonding layer and stopping at a level that the first bonding layer is in contact with the second bonding layer;
• removing the second wafer substrate;
• forming a second interconnect structure layer on the semiconductor component layer at a second side of semiconductor component layer, wherein the second interconnect structure layer is electrically connected to the first interconnect structure layer;
• forming a conductor terminal on the second interconnect structure layer;
• and
• performing a singulation process to obtain a semiconductor chip comprising the semiconductor component layer, the first interconnect structure layer, the second interconnect structure layer and the conductor terminal, wherein the air gap is separated from the semiconductor chip by the singulation process.