Built-in self-test circuits for memory systems having multiple channels
AssigneeSamsung Electronics Co., Ltd.
InventorsJaewon Park, Shinhaeng Kang
Life of this patent
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Abstract
A memory system includes a plurality of memory devices having respective arrays of memory cells therein, a bus electrically coupled to and shared by the plurality of memory devices, and a memory controller. The memory controller, which is electrically coupled to the bus, includes a built-in self-test (BIST) circuit, which is commonly connected to the plurality of memory devices. The BIST circuit is configured to transfer a command set including a test pattern to the plurality of memory devices via the bus, and transfer a command trigger signal for driving the test pattern to the plurality of memory devices via the bus.
Claims17
A memory system, comprising:
- a plurality of memory devices having respective arrays of memory cells therein;
- a bus electrically coupled to and shared by the plurality of memory devices;
- and
- a memory controller electrically coupled by the bus to the plurality of memory devices, said memory controller comprising a built-in self-test (BIST) circuit, which is configured to transfer a respective command set including a respective at least one test pattern to each of the plurality of memory devices via the bus, and transfer a command trigger signal for driving the respective at least one test pattern to each of the plurality of memory devices via the bus;
- and
- wherein each of the plurality of memory devices comprises a respective command generation circuit, which is configured to store the respective command set received from said BIST circuit and test a corresponding memory cell array based on the respective at least one test pattern, in response to the command trigger signal.
A memory device, comprising:
- a first memory channel coupled to a first memory die;
- a second memory channel coupled to a second memory die;
- and
- a buffer die configured to interface with the first and second memory dies via the first and second memory channels, with each of the first and second memory dies being stacked on the buffer die and comprising respective arrays of memory cells therein, said buffer comprising a built-in self-test (BIST) circuit, which is:
- (i) electrically coupled in common to the first and second memory channels, and (ii) configured to transfer a command set including a respective test pattern to the first and second memory dies via the first and second memory channels and transfer a command trigger signal for driving the respective test pattern to the first and second memory dies via the first and second memory channels;
- and
- wherein each of the first and second memory dies comprises a respective command generation circuit, which is configured to store the command set and test the corresponding memory cell array based on the respective test pattern, in response to the command trigger signal.
A method of testing first and second memory channels comprising respective memory cell arrays therein, using a built-in self-test (BIST) circuit commonly connected to at least the first and second memory channels, said method comprising:
- transferring a command set including a respective test pattern to the first and second memory channels via the BIST circuit;
- transferring a command trigger signal for driving the respective test patterns to the first and second memory channels via the BIST circuit;
- testing each of the first and second memory channels using the respective test patterns, which are different from each other, in response to the command trigger signal;
- comparing the respective test pattern to data read from the respective memory cell array, in each of the first and second memory channels;
- detecting a defective memory cell of the memory cell array in each of the first and second memory channels;
- and
- transferring a defective address of the defective memory cell in each of the first and second memory channels to the BIST circuit as a test result.
Dependencies are inferred from the claim text.