# US 12,225,833 B2 · Oxide-based resistive memory having a plasma-exposed bottom electrode

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- Number: US 12,225,833 B2
- Document ID: US12225833B2
- Status: Granted
- Kind: B2
- Application number: 18/164,125
- Filed: 2023-02-03
- Published: 2023-08-17
- Granted: 2025-02-11
- Earliest claimed: 2020-06-11
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Takashi Ando; Hiroyuki Miyazoe; Eduard Albert Cartier; Babar Khan; Youngseok Kim; Dexin Kong; Soon-Cheon Seo; Joel P. De Souza
- Web page: https://patentgrep.com/patent/US12225833B2

## CPC

- H10N 70/041: {Modification of switching materials after formation, e.g. doping (shaping H10N70/061)}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10N 70/021: {Formation of switching materials, e.g. deposition of layers}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/841: {Electrodes}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Embodiments of the invention provide a resistive switching device that includes a metal interconnect electrode and a charge-particle-treated memory stack over the metal interconnect electrode. The charge-particle-treated memory stack includes a plurality of layers that includes a top electrode, a bottom electrode, and a dielectric layer between the top electrode and the bottom electrode. The dielectric layer includes a portion of a blanket dielectric layer. The bottom electrode includes a portion of a blanket bottom electrode layer. The charge-particle-treated memory stack further includes a current-conducting filament characteristic that results from charge particle treatments applied while a top surface of the blanket dielectric layer is exposed and a top surface of the blanket bottom electrode is exposed.

## Claims

### Claim 1

A resistive switching device comprising:
a metal interconnect electrode; and
a charge-particle-treated memory stack over the metal interconnect electrode;
wherein the memory stack comprises a plurality of layers that includes a top electrode, a bottom electrode, and a dielectric layer between the top electrode and the bottom electrode;
wherein the dielectric layer comprises a portion of a blanket dielectric layer;
wherein the bottom electrode comprises a portion of a blanket bottom electrode layer; and
wherein the charge-particle-treated memory stack further comprises a current-conducting filament characteristic that results from charge particle treatments applied while a top surface of the blanket dielectric layer is exposed and a top surface of the blanket bottom electrode is exposed.

### Claim 2 (depends on 1)

The device of claim 1, wherein dimensions of the charge-particle-treated memory stack are larger than dimensions of the metal interconnect electrode.

### Claim 3 (depends on 2)

The device of claim 2, wherein the metal interconnect electrode is on a surface of a metal interconnect layer.

### Claim 4 (depends on 3)

The device of claim 3, the metal interconnect layer is formed in an inter-level dielectric over a substrate.

### Claim 5 (depends on 4)

The device of claim 4, wherein the memory stack comprises a filament-forming voltage characteristic determined based at least in part on the current-conducting filament characteristic.

### Claim 6 (depends on 1)

The device of claim 1, wherein the bottom electrode, the dielectric layer, and the top electrode define a Resistive Random Access Memory (RRAM) device memory stack.

### Claim 7 (depends on 2)

The device of claim 2 further comprising a spacer on a sidewall of the top electrode.

### Claim 8 (depends on 6)

The device of claim 6, wherein the spacer is positioned on a surface of the dielectric layer such that an outer sidewall of the spacer is coplanar to a sidewall of the bottom electrode, and wherein the spacer is configured to encapsulate the top electrode to prevent a short between the top electrode and the bottom electrode.

### Claim 9 (depends on 7)

The device of claim 7 further comprising a hard mask on a surface of the top electrode, the hard mask adjacent to an inner sidewall of the spacer, wherein the hard mask comprises a hard mask material selected from the group consisting of an oxygen containing layer, an oxygen devoid layer, and a composite dielectric film that is substantially devoid of oxygen.

### Claim 10 (depends on 1)

The device of claim 1, wherein:
the bottom electrode comprises a hard mask material selected from the group consisting of an oxygen containing layer, an oxygen devoid layer, and a composite dielectric film that is substantially devoid of oxygen;
the dielectric layer comprises hafnium oxide; and
the top electrode comprises titanium nitride.

### Claim 11

A resistive switching device comprising:
a memory stack comprising a plurality of layers that includes a top electrode, a bottom electrode, and a dielectric layer between the top electrode and the bottom electrode; and
a spacer on a sidewall of at least a portion of the memory stack;
wherein the dielectric layer comprises a portion of a blanket dielectric layer;
wherein the bottom electrode comprises a portion of a blanket bottom electrode layer;
wherein the dielectric layer comprises a current-conducting filament characteristic that results from a charge particle treatment applied while a top surface of the blanket dielectric layer is exposed and a top surface of the blanket bottom electrode is exposed; and
wherein the spacer prevents a short between the top electrode and the bottom electrode.

### Claim 12 (depends on 11)

The device of claim 11, wherein dimensions of the charge-particle-treated memory stack are larger than dimensions of the metal interconnect electrode.

### Claim 13 (depends on 12)

The device of claim 12, wherein the metal interconnect electrode is on a surface of a metal interconnect layer.

### Claim 14 (depends on 13)

The device of claim 13, the metal interconnect layer is formed in an inter-level dielectric over a substrate.

### Claim 15 (depends on 14)

The device of claim 14, wherein the charge-particle-treated memory stack comprises a filament-forming voltage characteristic determined based at least in part on the current-conducting filament characteristic.

### Claim 16 (depends on 11)

The device of claim 11, wherein the bottom electrode, the dielectric layer, and the top electrode define a Resistive Random Access Memory (RRAM) device memory stack.

### Claim 17 (depends on 12)

The device of claim 12, wherein the portion of the memory stack comprises a sidewall of the top electrode.

### Claim 18 (depends on 17)

The device of claim 17, wherein the spacer is positioned on a surface of the dielectric layer such that an outer sidewall of the spacer is coplanar to a sidewall of the bottom electrode, and wherein the spacer is configured to encapsulate the top electrode to prevent a short between the top electrode and the bottom electrode.

### Claim 19 (depends on 18)

The device of claim 18 further comprising a hard mask on a surface of the top electrode, the hard mask adjacent to an inner sidewall of the spacer, wherein the hard mask comprises tantalum nitride.

### Claim 20 (depends on 11)

The device of claim 11, wherein:
the bottom electrode comprises a hard mask material selected from the group consisting of an oxygen containing layer, an oxygen devoid layer, and a composite dielectric film that is substantially devoid of oxygen;
the dielectric layer comprises hafnium oxide; and
the top electrode comprises titanium nitride.