# US 12,225,781 B2 · Array substrate and display apparatus

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- Number: US 12,225,781 B2
- Document ID: US12225781B2
- Status: Granted
- Kind: B2
- Application number: 17/788,605
- Filed: 2021-08-30
- Published: 2024-06-27
- Granted: 2025-02-11
- Earliest claimed: 2021-03-11
- Assignees: Boe Technology Group Co., Ltd.
- Applicants: BOE Technology Group Co., Ltd.
- Inventors: Yu Feng; Libin Liu; Jiangnan Lu
- Web page: https://patentgrep.com/patent/US12225781B2

## CPC

- H10K 59/1213: {the pixel elements being TFTs}
- H10K 59/124: Insulating layers formed between TFT elements and OLED elements
- G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED]
- G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6756: {Amorphous oxide semiconductors}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H10K 59/1216: {the pixel elements being capacitors}
- H10K 59/131: Interconnections, e.g. wiring lines or terminals
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing
- G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
- G09G 2310/0251: Precharge or discharge of pixel before applying new pixel voltage
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2320/0233: Improving the luminance or brightness uniformity across the screen
- G09G 2320/0247: Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An array substrate is provided. A respective pixel driving circuit of the array substrate includes a driving transistor, a storage capacitor, and a transistor having a gate electrode connected to a respective second gate line of a plurality of second gate lines, a first electrode connected to a first capacitor electrode of the storage capacitor, and a second electrode connected to a second electrode of a first reset transistor, the transistor being configured to receive a reset signal through the first reset transistor. An active layer of the driving transistor and an active layer of the transistor are spaced apart from each other by at least an insulating layer. The active layer of the driving transistor comprises a first semiconductor material. The active layer of the transistor comprises a second semiconductor material different from the first semiconductor material.

## Claims

### Claim 1

An array substrate, comprising a plurality of pixel driving circuits, a plurality of light emitting elements respectively connected to the plurality of pixel driving circuits, and a first connecting pad in a first signal line layer, the first connecting pad connecting the second electrode of the transistor and the second electrode of the first reset transistor;
wherein a respective pixel driving circuit comprises a driving transistor, a storage capacitor, and a transistor having a gate electrode connected to a respective second gate line of a plurality of second gate lines, a first electrode connected to a first capacitor electrode of the storage capacitor, and a second electrode connected to a second electrode of a first reset transistor, the transistor being configured to receive a reset signal through the first reset transistor;
an active layer of the driving transistor and an active layer of the transistor are spaced apart from each other by at least an insulating layer;
the active layer of the driving transistor comprises a first semiconductor material; and
the active layer of the transistor comprises a second semiconductor material different from the first semiconductor material;
wherein the first connecting pad is connected to the second electrode of the transistor through a first via extending through at least a passivation layer, and is connected to the second electrode of the first reset transistor through a second via extending through at least the passivation layer and the insulating layer.

### Claim 2 (depends on 1)

The array substrate of claim 1, wherein gate electrodes of the transistor and the first reset transistor are connected to different control signal lines in different layers, respectively.

### Claim 3 (depends on 1)

The array substrate of claim 1, wherein the respective pixel driving circuit further comprises the first reset transistor comprising a gate electrode connected to a respective reset control signal line in a present stage of a plurality of reset control signal lines, a first electrode connected to a respective first reset signal line of a plurality of first reset signal lines, and a second electrode connected to the second electrode of the transistor.

### Claim 4 (depends on 1)

The array substrate of claim 1, further comprising a node connecting line in the first signal line layer;
wherein the node connecting line connects the first electrode of the transistor to the first capacitor electrode, which functions as a gate electrode of the driving transistor.

### Claim 5

An array substrate, comprising a plurality of pixel driving circuits, a plurality of light emitting elements respectively connected to the plurality of pixel driving circuits, a node connecting line in the first signal line layer, and an auxiliary capacitor electrode;
wherein a respective pixel driving circuit comprises a driving transistor, a storage capacitor, and a transistor having a gate electrode connected to a respective second gate line of a plurality of second gate lines, a first electrode connected to a first capacitor electrode of the storage capacitor, and a second electrode connected to a second electrode of a first reset transistor, the transistor being configured to receive a reset signal through the first reset transistor;
an active layer of the driving transistor and an active layer of the transistor are spaced apart from each other by at least an insulating layer;
the active layer of the driving transistor comprises a first semiconductor material; and
the active layer of the transistor comprises a second semiconductor material different from the first semiconductor material;
wherein the node connecting line connects the first electrode of the transistor to the first capacitor electrode, which functions as a gate electrode of the driving transistor;
wherein the node connecting line is connected to the auxiliary capacitor electrode through a fifth via extending through at least a passivation layer; and
wherein the array substrate further comprises an auxiliary capacitor comprising the auxiliary capacitor electrode and a portion of a respective first gate line of a plurality of first gate lines, the respective first gate line being connected to a gate electrode of a first transistor and a gate electrode of a second transistor.

### Claim 6 (depends on 4)

The array substrate of claim 4, wherein the node connecting line crosses over the respective second gate line in a present stage.

### Claim 7

An array substrate, comprising a plurality of pixel driving circuits, a plurality of light emitting elements respectively connected to the plurality of pixel driving circuits, and a node connecting line in a first signal line layer;
wherein a respective pixel driving circuit comprises a driving transistor, a storage capacitor, and a transistor having a gate electrode connected to a respective second gate line of a plurality of second gate lines, a first electrode connected to a first capacitor electrode of the storage capacitor, and a second electrode connected to a second electrode of a first reset transistor, the transistor being configured to receive a reset signal through the first reset transistor;
an active layer of the driving transistor and an active layer of the transistor are spaced apart from each other by at least an insulating layer;
the active layer of the driving transistor comprises a first semiconductor material; and
the active layer of the transistor comprises a second semiconductor material different from the first semiconductor material;
wherein the respective second gate line comprises a first branch and a second branch respectively in two different layers;
the first branch is in a same layer as a second capacitor electrode of the storage capacitor;
the second branch is in a same layer as a plurality of first reset signal lines, a respective first reset signal line of the plurality of first reset signal lines is configured to provide a reset signal to the first electrode of the transistor; and
the node connecting line crosses over the first branch and the second branch in a present stage.

### Claim 8 (depends on 1)

The array substrate of claim 1, wherein the respective pixel driving circuit further comprises a second transistor comprising a gate electrode connected to a respective first gate line of a plurality of first gate lines, a first electrode connected to the second electrode of the transistor and the second electrode of the first reset transistor, and a second electrode connected to a second electrode of a driving transistor.

### Claim 9 (depends on 8)

The array substrate of claim 8, wherein the respective first gate line is in a layer different from the respective second gate line; and
the respective first gate line is in a same layer as a plurality of reset control signal lines, a respective reset control signal line in a present stage of a plurality of reset control signal lines being connected to a gate electrode of the first reset transistor.

### Claim 10 (depends on 1)

The array substrate of claim 1, wherein the respective pixel driving circuit further comprises:
the first reset transistor comprising a gate electrode connected to a respective reset control signal line in a present stage of a plurality of reset control signal lines, a first electrode connected to a respective first reset signal line of a plurality of first reset signal lines, and a second electrode connected to the second electrode of the transistor; and
a second reset transistor comprising a gate electrode connected to a respective reset control signal line in a next stage of a plurality of reset control signal lines, a first electrode connected to a respective second reset signal line of a plurality of second reset signal lines, and a second electrode connected to an anode of a respective light emitting element of the plurality of light emitting elements.

### Claim 11 (depends on 10)

The array substrate of claim 10, wherein the plurality of first reset signal lines are in a same layer as a second branch of the respective second gate line; and
the plurality of second reset signal lines are in a same layer as a first connecting pad in a first signal line layer.

### Claim 12 (depends on 1)

The array substrate of claim 1, further comprising a second connecting pad in a first signal line layer, the second connecting pad connecting the first electrode of the first reset transistor and a respective first reset signal line of a plurality of first reset signal lines.

### Claim 13 (depends on 1)

The array substrate of claim 1, wherein the respective pixel driving circuit further comprises a second reset transistor comprising a gate electrode connected to a respective reset control signal line in a next stage of a plurality of reset control signal lines, a first electrode connected to a respective second reset signal line of a plurality of second reset signal lines, and a second electrode connected to an anode of a respective light emitting element of the plurality of light emitting elements; and
wherein the first electrode of the second reset transistor and a first electrode of a second reset transistor in an adjacent pixel driving circuit are connected to each other, forming a unitary structure, the respective pixel driving circuit and the adjacent pixel driving circuit being directly adjacent to each other and in the present stage.

### Claim 14 (depends on 1)

The array substrate of claim 1, further comprising a light shield in a light shield layer and an auxiliary capacitor electrode;
wherein an orthographic projection of the light shield on a base substrate covers at least 50% of an orthographic projection of an active layer of the driving transistor on the base substrate;
the orthographic projection of the light shield on the base substrate covers at least 50% of an orthographic projection of the first capacitor electrode on the base substrate;
the storage capacitor comprises the first capacitor electrode and a second capacitor electrode;
the orthographic projection of the light shield on the base substrate covers at least 50% of an orthographic projection of the second capacitor electrode on the base substrate;
the auxiliary capacitor electrode and a portion of a respective first gate line of a plurality of first gate lines are configured to form an auxiliary capacitor, the respective first gate line being connected to a gate electrode of a first transistor and a gate electrode of a second transistor; and
the orthographic projection of the light shield on the base substrate covers at least 50% of an orthographic projection of the auxiliary capacitor electrode on the base substrate.

### Claim 15 (depends on 1)

The array substrate of claim 1, further comprising:
a first connecting pad in a first signal line layer, the first connecting pad connecting the second electrode of the transistor and the second electrode of the first reset transistor; and
a plurality of voltage supply lines;
wherein an orthographic projection of a respective voltage supply line of the plurality of voltage supply lines on a base substrate covers at least 50% of an orthographic projection of the first connecting pad on the base substrate.

### Claim 16 (depends on 1)

The array substrate of claim 1, further comprising:
an auxiliary capacitor electrode;
a node connecting line in a first signal line layer; and
a plurality of voltage supply lines;
wherein the node connecting line is connected to the auxiliary capacitor electrode through a fifth via extending through at least the passivation layer;
the auxiliary capacitor electrode and a portion of a respective first gate line of a plurality of first gate lines are configured to form an auxiliary capacitor, the respective first gate line being connected to a gate electrode of a first transistor and a gate electrode of a second transistor; and
an orthographic projection of a respective voltage supply line of the plurality of voltage supply lines on a base substrate covers at least 50% of an orthographic projection of the auxiliary capacitor electrode on the base substrate.

### Claim 17 (depends on 1)

The array substrate of claim 1, further comprising:
a plurality of voltage supply lines;
an auxiliary capacitor electrode;
a node connecting line in a first signal line layer;
a plurality of voltage supply lines; and
a first connecting pad in the first signal line layer;
wherein a first respective voltage supply line and a second respective voltage supply line respectively connected to a first pixel driving circuit and a second pixel driving circuit are connected to each other, forming a unitary structure, the first pixel driving circuit and the second pixel driving circuit being directly adjacent to each other and in the present stage;
the node connecting line connects the first electrode of the transistor to the first capacitor electrode, which functions as a gate electrode of the driving transistor;
the first connecting pad connects the second electrode of the transistor and the second electrode of the first reset transistor;
the node connecting line is connected to the auxiliary capacitor electrode through a fifth via extending through at least a passivation layer;
the auxiliary capacitor electrode and a portion of a respective first gate line of a plurality of first gate lines are configured to form an auxiliary capacitor, the respective first gate line being connected to a gate electrode of a first transistor and a gate electrode of a second transistor; and
an orthographic projection of the unitary structure on a base substrate covers at least 50% of an orthographic projection of active layers of transistors respectively of the first pixel driving circuit and the second pixel driving circuit on the base substrate, covers at least 50% of an orthographic projection of node connecting lines respectively of the first pixel driving circuit and the second pixel driving circuit on the base substrate, covers at least 50% of an orthographic projection of first connecting pads respectively of the first pixel driving circuit and the second pixel driving circuit on the base substrate, and covers at least 50% of an orthographic projection of auxiliary capacitor electrodes respectively of the first pixel driving circuit and the second pixel driving circuit on the base substrate.

### Claim 18 (depends on 1)

A display apparatus, comprising the array substrate of claim 1, and an integrated circuit connected to the array substrate.