# US 12,225,740 B2 · Dual metal silicide structures for advanced integrated circuit structure fabrication

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- Number: US 12,225,740 B2
- Document ID: US12225740B2
- Status: Granted
- Kind: B2
- Application number: 18/435,609
- Filed: 2024-02-07
- Published: 2024-05-30
- Granted: 2025-02-11
- Earliest claimed: 2017-11-30
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Jeffrey S. Leib; Srijit Mukherjee; Vinay Bhagwat; Michael L. Hattendorf; Christopher P. Auth
- Web page: https://patentgrep.com/patent/US12225740B2

## CPC

- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10B 10/12: {comprising a MOSFET load element}
- H10D 1/474: {comprising refractory metals, transition metals, noble metals, metal compounds or metal alloys, e.g. silicides}
- H10D 30/6213: {having rounded corners}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 30/795: {being in lateral device isolation regions, e.g. STI}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/01354: {passivation or protection of the electrode, e.g. using re-oxidation}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/689: {having ferroelectric layers}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D 84/853: {comprising FinFETs}
- H10P 14/418: {the conductive layers comprising transition metals}
- H10P 50/282: {of inorganic materials}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 50/73: {using masks for insulating materials}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.

## Claims

### Claim 1

An integrated circuit structure, comprising:
a first semiconductor device, the first semiconductor device comprising:
first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode, respectively, the first and second semiconductor source or drain regions comprising a layer comprising germanium; and
a first metal silicide layer directly on the layer comprising germanium of the first and second semiconductor source or drain regions, wherein the first metal silicide layer comprises nickel, platinum and silicon; and
a second N-type semiconductor device, the second semiconductor device comprising:
third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode, respectively; and
a second metal silicide layer directly on the third and fourth semiconductor source or drain regions, respectively, wherein the second metal silicide layer comprises titanium and silicon, the second metal silicide layer having a different composition than the first metal silicide layer.

### Claim 2 (depends on 1)

The integrated circuit structure of claim 1, wherein the first metal silicide layer further comprises germanium.

### Claim 3 (depends on 1)

The integrated circuit structure of claim 1, wherein the first metal silicide layer further comprises titanium.

### Claim 4 (depends on 1)

The integrated circuit structure of claim 1, wherein the first metal silicide layer further comprises germanium and titanium.

### Claim 5 (depends on 1)

The integrated circuit structure of claim 1, wherein the first and second semiconductor source or drain regions are first and second embedded semiconductor source or drain regions, and the third and fourth semiconductor source or drain regions are third and fourth embedded semiconductor source or drain regions comprising silicon.

### Claim 6 (depends on 1)

The integrated circuit structure of claim 1, further comprising:
a first semiconductor fin, wherein the first gate electrode is over a channel region of the first semiconductor fin; and
a second semiconductor fin, wherein the second gate electrode is over a channel region of the second semiconductor fin.

### Claim 7 (depends on 1)

The integrated circuit structure of claim 1, further comprising:
a first semiconductor nanowire, wherein the first gate electrode completely surrounds a channel region of the first semiconductor nanowire; and
a second semiconductor nanowire, wherein the second gate electrode completely surrounds a channel region of the second semiconductor nanowire.

### Claim 8 (depends on 1)

The integrated circuit structure of claim 1, wherein the first semiconductor device is a P-type semiconductor device.

### Claim 9 (depends on 1)

The integrated circuit structure of claim 1, wherein the second semiconductor device is an N-type semiconductor device.

### Claim 10 (depends on 1)

The integrated circuit structure of claim 1, wherein the first semiconductor device is a P-type semiconductor device, and wherein the second semiconductor device is an N-type semiconductor device.

### Claim 11

A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first semiconductor device, the first semiconductor device comprising:
first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode, respectively, the first and second semiconductor source or drain regions comprising a layer comprising germanium; and
a first metal silicide layer directly on the layer comprising germanium of the first and second semiconductor source or drain regions, wherein the first metal silicide layer comprises nickel, platinum and silicon; and
a second N-type semiconductor device, the second semiconductor device comprising:
third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode, respectively; and
a second metal silicide layer directly on the third and fourth semiconductor source or drain regions, respectively, wherein the second metal silicide layer comprises titanium and silicon, the second metal silicide layer having a different composition than the first metal silicide layer.

### Claim 12 (depends on 11)

The computing device of claim 11, further comprising:
a memory coupled to the board.

### Claim 13 (depends on 11)

The computing device of claim 11, further comprising:
a communication chip coupled to the board.

### Claim 14 (depends on 11)

The computing device of claim 11, further comprising:
a camera coupled to the board.

### Claim 15 (depends on 11)

The computing device of claim 11, further comprising:
a battery coupled to the board.

### Claim 16 (depends on 11)

The computing device of claim 11, further comprising:
an antenna coupled to the board.

### Claim 17 (depends on 11)

The computing device of claim 11, wherein the component is a packaged integrated circuit die.

### Claim 18 (depends on 11)

The computing device of claim 11, wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.

### Claim 19 (depends on 11)

The computing device of claim 11, wherein the integrated circuit structure further comprises:
a first semiconductor fin, wherein the first gate electrode is over a channel region of the first semiconductor fin; and
a second semiconductor fin, wherein the second gate electrode is over a channel region of the second semiconductor fin.

### Claim 20 (depends on 11)

The computing device of claim 11, wherein the integrated circuit structure further comprises:
a first semiconductor nanowire, wherein the first gate electrode completely surrounds a channel region of the first semiconductor nanowire; and
a second semiconductor nanowire, wherein the second gate electrode completely surrounds a channel region of the second semiconductor nanowire.