# US 12,225,735 B2 · Selector for memory device

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- Number: US 12,225,735 B2
- Document ID: US12225735B2
- Status: Granted
- Kind: B2
- Application number: 17/833,907
- Filed: 2022-06-07
- Published: 2023-12-07
- Granted: 2025-02-11
- Earliest claimed: 2022-06-07
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Hung-Ju Li; Kuo-Pin Chang; Yu-Wei Ting; Ching-En Chen; Kuo-Ching Huang
- Web page: https://patentgrep.com/patent/US12225735B2

## CPC

- H10B 63/24: {of the Ovonic threshold switching type}
- H10B 63/20: {comprising selection components having two electrodes, e.g. diodes}
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/882: {Compounds of sulfur, selenium or tellurium, e.g. chalcogenides}
- H10N 70/883: {Oxides or nitrides}
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A memory device is provided in various embodiments. The memory device, in those embodiments, has an ovonic threshold switching (OTS) selector comprising multiple layers of OTS materials to achieve a low leakage current and as well as relatively low threshold voltage for the OTS selector. The multiple layers can have at least one layer of low bandgap OTS material and at least one layer of high bandgap OTS material.

## Claims

### Claim 1

A memory device comprising:
a first metallic layer;
a first low bandgap ovonic threshold switching (OTS) layer disposed in direct contact with the first metallic layer;
a high bandgap OTS layer disposed adjacent to the first low bandgap OTS layer and in direct contact with the first low bandgap OTS layer;
a second low bandgap OTS layer disposed adjacent to the high bandgap OTS layer and in direct contact with the high bandgap OTS layer; and
a second metallic layer disposed adjacent to the second low bandgap OTS layer and in direct contact with the second low bandgap OTS layer; and, wherein the first metallic layer, the first low bandgap OTS layer, the high bandgap OTS layer, the second low bandgap OTS layer and the second metallic layer forming a phase change element arranged to have a threshold voltage to operate with a corresponding leakage current.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the first low bandgap OTS layer and the second low bandgap OTS layer have substantially the same thickness.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein a ratio of a thickness of the first low bandgap OTS layer to a thickness of the high bandgap OTS layer is 0.01 to 100.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein the first low bandgap OTS layer and the second low bandgap OTS layer have different thicknesses.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein the first low bandgap OTS layer or the second low bandgap OTS layer comprises at least one selected from the group consisting of GeSe, SiTe/CTe, and GeAsSeTeSi.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the high bandgap OTS layer comprises at least one selected from a group comprises GeTe, ZnTe, and GeAsTeSiN.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the first low bandgap OTS layer or the second low bandgap OTS layer comprises at least one selected from a group comprising GeSe and GeTe, and the high bandgap OTS layer consists of at least one selected from a group comprising GeSeN, GeSeAs, and GeTeN.

### Claim 8

A method for forming a memory device, the method comprising:
forming a first metallic layer;
disposing a first low bandgap ovonic threshold switching (OTS) layer in direct contact with the first metallic layer;
disposing a high bandgap OTS layer disposed adjacent to the first low bandgap OTS layer in direct contact with the first low bandgap OTS layer;
disposing a second low bandgap OTS layer adjacent to the high bandgap OTS layer in direct contact with the high bandgap OTS layer; and
disposing a second metallic layer adjacent to the second low bandgap OTS layer in direct contact with the second low bandgap OTS layer; and, wherein the first metallic layer, the first low bandgap OTS layer, the high bandgap OTS layer, the second low bandgap OTS layer and the second metallic layer forming a phase change element arranged to have a threshold voltage to operate with a corresponding leakage current.

### Claim 9 (depends on 8)

The method of claim 8, wherein the first low bandgap OTS layer and the second low bandgap OTS layer have substantially the same thickness.

### Claim 10 (depends on 9)

The method of claim 9, wherein a ratio of a thickness of the first low bandgap OTS layer to a thickness of the high bandgap OTS layer is 0.01 to 100.

### Claim 11 (depends on 8)

The method of claim 8, wherein the first low bandgap OTS layer and the second low bandgap OTS layer have different thicknesses.

### Claim 12 (depends on 8)

The method of claim 8, wherein the first low bandgap OTS layer or the second low bandgap OTS layer comprises at least one selected from a group comprising GeSe, SiTe/CTe, and GeAsSeTeSi.

### Claim 13 (depends on 8)

The method of claim 8, wherein the high bandgap OTS layer comprises at least one selected from a group comprising GeTe, ZnTe, and GeAsTeSiN.

### Claim 14 (depends on 8)

The method of claim 8, wherein the first low bandgap OTS layer or the second low bandgap OTS layer comprises at least one selected from a group comprising GeSe and GeTe, and the high bandgap OTS layer consists of at least one selected from a group comprising GeSeN, GeSeAs, and GeTeN.

### Claim 15

A memory array comprising:
bit lines including a first bit line, word lines including a first word line, and memory devices including a first memory device, wherein the first memory device is located at an intersection of the first bit line intersecting the first world line, and wherein the first memory device comprises a phase change memory connected to an ovonic threshold switching (OTS) selector, wherein the OTS selector comprises:
a first metallic layer;
a first low bandgap OTS layer disposed in direct contact with the first metallic layer;
a high bandgap OTS layer disposed adjacent to the first low bandgap OTS layer and in direct contact with the first low bandgap OTS layer;
a second low bandgap OTS layer disposed adjacent to the high bandgap OTS layer and in direct contact with the high bandgap OTS layer; and
a second metallic layer disposed adjacent to the second low bandgap OTS layer and in direct contact with the second low bandgap OTS layer; and, wherein the first metallic layer, the first low bandgap OTS layer, the high bandgap OTS layer, the second low bandgap OTS layer and the second metallic layer forming a phase change element arranged to have a threshold voltage to operate with a corresponding leakage current.

### Claim 16 (depends on 15)

The memory array of claim 15, wherein the first low bandgap OTS layer and the second low bandgap OTS layer have substantially the same thickness.

### Claim 17 (depends on 16)

The memory array of claim 16, wherein a ratio of a thickness of the first low bandgap OTS layer to a thickness of the high bandgap OTS layer is 0.01 to 100.

### Claim 18 (depends on 15)

The memory array of claim 15, wherein the first low bandgap OTS layer and the second low bandgap OTS layer have different thicknesses.

### Claim 19 (depends on 15)

The memory array of claim 15, wherein the first low bandgap OTS layer or the second low bandgap OTS layer comprising at least one selected from a group of GeSe, SiTe/CTe, and GeAsSeTeSi.

### Claim 20 (depends on 15)

The memory array of claim 15, wherein the high bandgap OTS layer comprising at least one selected from a group of GeTe, ZnTe, and GeAsTeSiN.