# US 12,225,731 B2 · Memory array contact structures

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- Number: US 12,225,731 B2
- Document ID: US12225731B2
- Status: Granted
- Kind: B2
- Application number: 17/818,638
- Filed: 2022-08-09
- Published: 2022-12-01
- Granted: 2025-02-11
- Earliest claimed: 2020-06-25
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chih-Yu Chang; Meng-Han Lin; Sai-Hooi Yeong; Bo-Feng Young; Yu-Ming Lin
- Web page: https://patentgrep.com/patent/US12225731B2

## CPC

- H10B 51/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- G11C 11/223: {using MOS with ferroelectric gate insulating film}
- G11C 11/2255: {Bit-line or column circuits}
- G11C 11/2259: {Cell access}
- H10B 51/10: characterised by the top-view layout
- H10B 51/30: characterised by the memory core region
- H10B 51/50: characterised by the boundary region between the core and peripheral circuit regions
- H10D 30/026: {having laterally-coplanar source and drain regions, a gate at the sides of the bulk channel, and both horizontal and vertical current flow (of LDMOS H10D30/0289)}
- H10D 30/0415: {of FETs having ferroelectric gate insulators}
- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 64/033: {comprising ferroelectric layers}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10B 43/10: characterised by the top-view layout
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A memory cell includes a transistor including a memory film extending along a word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; a source line extending along the memory film, wherein the memory film is between the source line and the word line; a first contact layer on the source line, wherein the first contact layer contacts the channel layer and the memory film; a bit line extending along the memory film, wherein the memory film is between the bit line and the word line; a second contact layer on the bit line, wherein the second contact layer contacts the channel layer and the memory film; and an isolation region between the source line and the bit line.

## Claims

### Claim 1

A method comprising:
forming a multi-layer stack comprising a plurality of word lines;
depositing a memory film on a sidewall of the multi-layer stack;
forming a first channel region and a second channel region on the memory film;
depositing a contact layer on the memory film, on the first channel region, and on the second channel region;
depositing a conductive material on the contact layer;
etching a first trench in the contact layer and conductive material, wherein the trench separates a first portion of the contact layer and a first portion of the conductive material from a second portion of the contact layer and a second portion of the conductive material, wherein the first portion contacts the first channel region and the second portion contacts the second channel region; and
depositing an insulating material in the first trench.

### Claim 2 (depends on 1)

The method of claim 1 further comprising depositing an isolation material on the memory film.

### Claim 3 (depends on 2)

The method of claim 2 further comprising etching a second trench in the isolation material, wherein the contact layer is deposited in the second trench.

### Claim 4 (depends on 1)

The method of claim 1, wherein before etching the first trench, the contact layer encircles the conductive material.

### Claim 5 (depends on 1)

The method of claim 1, wherein the first trench has an oval shape.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first portion of the contact layer and the first portion of the conductive material form a bit line, wherein the second portion of the contact layer and the second portion of the conductive material form a source line.

### Claim 7 (depends on 1)

The method of claim 1, wherein the memory film is a ferroelectric material.

### Claim 8 (depends on 1)

The method of claim 1, wherein the contact layer, the first channel region, and the second channel region are the same material.

### Claim 9 (depends on 1)

The method of claim 1, wherein a length of the first trench is greater than a length of the first portion of the conductive material.

### Claim 10

A method comprising:
forming a first ferroelectric layer over a first sidewall of a first word line and a second ferroelectric layer on a second sidewall of a second word line;
forming a first oxide semiconductor (OS) layer over the first ferroelectric layer and a second OS layer over the second ferroelectric layer;
forming a first dielectric material extending between the first OS layer and the second OS layer;
removing a first portion of the first dielectric material, a first portion of the first OS layer adjacent the first portion of the first dielectric material, and a second portion of the second OS layer adjacent the first portion of the first dielectric material to form a first recess;
depositing a refill layer in the first recess;
depositing a conductive material on the refill layer;
removing a first portion of the conductive material, a first portion of the refill layer between the first portion of the conductive material and the first ferroelectric layer, and a second portion of the refill layer between the first portion of the conductive material and the second ferroelectric layer to form a second recess; and
filling the second recess with a second dielectric material.

### Claim 11 (depends on 10)

The method of claim 10, wherein the refill layer physically contacts the first ferroelectric layer and the second ferroelectric layer.

### Claim 12 (depends on 10)

The method of claim 10, wherein the refill layer is between the first dielectric material and the conductive material.

### Claim 13 (depends on 10)

The method of claim 10, wherein the conductive material physically contacts the first dielectric material.

### Claim 14 (depends on 10)

The method of claim 10, wherein the first ferroelectric layer is formed over a third word line that is above the first word line.

### Claim 15 (depends on 10)

The method of claim 10, wherein the refill layer comprises a different oxide semiconductor than the OS layer.

### Claim 16 (depends on 10)

The method of claim 10, wherein removing the first portion of the first OS layer exposes the first ferroelectric layer.

### Claim 17

A method comprising:
patterning a first trench extending through a first conductive line;
depositing a memory film along sidewalls and a bottom surface of the first trench;
depositing an oxide semiconductor (OS) layer over the memory film, wherein the OS layer extends along the sidewalls and the bottom surface of the first trench;
depositing a first dielectric material on the OS layer, wherein the first dielectric material fills the remaining portion of the first trench;
patterning a second trench in the first dielectric material and the OS layer, wherein patterning the second trench exposes a sidewall surface of the memory film and a sidewall surface of the OS layer;
depositing a refill layer along sidewalls and a bottom surface of the second trench, wherein the refill layer physically contacts the sidewall surface of the OS layer;
depositing a conductive material on the refill layer, wherein the conductive material fills the remaining portion of the second trench;
patterning a third trench in the conductive material and the refill layer, wherein patterning the third trench exposes the sidewall surface of the memory film and a sidewall surface of the refill layer; and
depositing a second dielectric material in the third trench, wherein the second dielectric material fills the third trench.

### Claim 18 (depends on 17)

The method of claim 17, wherein depositing the refill layer comprises performing a selective deposition process that selectively deposits the refill layer on surfaces of the memory film and on surfaces of the OS layer more than on surfaces of the first dielectric material.

### Claim 19 (depends on 17)

The method of claim 17, wherein the refill layer has a different composition than the OS layer.

### Claim 20 (depends on 17)

The method of claim 17, wherein the refill layer is deposited to a different thickness than the OS layer.