Three-dimensional semiconductor memory device and electronic system including the same

A three-dimensional semiconductor memory device, comprising:

• a first substrate comprising a cell array region and an extension region;
• a peripheral circuit structure comprising a peripheral circuit on the first substrate;
• a second substrate on the peripheral circuit structure;
• and
• a cell array structure on the second substrate,
• wherein the cell array structure comprises:
• a plurality of stack structures which extend in a first direction and comprise a plurality of gate electrodes and a plurality of interlayer dielectric layers which are alternately stacked on the second substrate;
• a plurality of vertical structures which penetrate the stack structures on the cell array region;
• respective bit-line contact plugs connected to respective ones of the vertical structures;
• respective cell contact plugs connected to respective ones of the gate electrodes on the extension region;
• a mold structure on a portion of the extension region;
• a peripheral connection contact plug which penetrates the mold structure and the second substrate, and is electrically connected to the peripheral circuit structure;
• a first support structure which extends in the first direction between the stack structures;
• a plurality of second support structures which penetrate the stack structures on the extension region and are spaced apart in a second direction from the first support structure, the second direction intersecting the first direction;
• and
• a third support structure which surrounds the mold structure in a plan view,
• wherein top surfaces of ones of the second support structures and a top surface of the third support structure are higher than top surfaces of ones of the vertical structures with respect to the second substrate defining a base reference level,
• wherein the ones of the second support structures and the third support structure each comprise a spacer part and a filler part that is in a space surrounded by the spacer part in a plan view, and
• wherein a top surface of the first support structure is higher than the top surfaces of the ones of the second support structures and the top surface of the third support structure with respect to the second substrate defining the base reference level.

An electronic system, comprising:

• a main board;
• a three-dimensional semiconductor memory device on the main board;
• and
• a controller on the main board that is electrically connected to the three-dimensional semiconductor memory device,
• wherein the three-dimensional semiconductor memory device comprises:
• a first substrate comprising a cell array region and an extension region;
• a peripheral circuit structure comprising a peripheral circuit on the first substrate;
• a second substrate on the peripheral circuit structure;
• a plurality of stack structures which extend in a first direction and comprise a plurality of gate electrodes stacked on the second substrate;
• a plurality of vertical structures which penetrate the stack structures on the cell array region;
• a mold structure on a portion of the extension region;
• a first support structure which extends in the first direction between the stack structures;
• a plurality of second support structures which penetrate the stack structures on the extension region and are spaced apart in a second direction from the first support structure, the second direction intersecting the first direction;
• a third support structure which surrounds the mold structure in plan view;
• and
• an input/output pad electrically connected to the peripheral circuit,
• wherein respective top surfaces of ones of the second support structures and a top surface of the third support structure are higher than a top surfaces of ones of the vertical structures with respect to the second substrate defining a base reference level, and
• wherein a bottom surface of the first support structure, respective bottom surfaces of the second support structures and a bottom surface of the third support structure are between a bottom surface of a lowermost one of the gate electrodes and a bottom surface of ones of the plurality of vertical structures.