# US 12,225,728 B2 · Method for fabricating semiconductor memory device including channel posts of different shapes

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- Number: US 12,225,728 B2
- Document ID: US12225728B2
- Status: Granted
- Kind: B2
- Application number: 18/306,092
- Filed: 2023-04-24
- Published: 2023-08-17
- Granted: 2025-02-11
- Earliest claimed: 2020-04-20
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Sung Wook Jung
- Web page: https://patentgrep.com/patent/US12225728B2

## CPC

- H10B 43/30: characterised by the memory core region
- H10B 43/10: characterised by the top-view layout
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor memory device includes an electrode structure, a plurality of channel posts, and at least one gate separation layer. The electrode structure includes insulating interlayers and gate conductive layers which are alternately stacked. The channel posts are formed through the electrode structure. The gate separation layer is formed between the channel posts. The gate separation layer separates an uppermost gate conductive layer among the gate conductive layers. Each channel post among the channel posts adjacent to the gate separation layer has a gibbous moon shape in a planar view. The semiconductor memory device further includes a slit structure arranged at both sides of the gate separation layer. The slit structure is formed through the electrode structure. Each channel post among the channel posts adjacent to the slit structure has a gibbous moon shape in the planar view.

## Claims

### Claim 1

A method of manufacturing a semiconductor memory device, the method comprising:
alternately stacking a plurality of insulating interlayers that are alternately stacked with a plurality of sacrificial layers to form a stack structure;
selectively etching the stack structure to form a gate separation layer configured to separate an uppermost sacrificial layer among the plurality of sacrificial layers;
forming a plurality of channel posts through the stack structure, channel posts among the plurality of the channel posts adjacent to the gate separation layer having a first curved portion and a second curved portion having a curvature different from a curvature of the first curved portion in a planar view; and
replacing the plurality of sacrificial layers by a plurality of gate conductive layers.

### Claim 2 (depends on 1)

The method of claim 1, further comprising forming a slit structure through the stack structure at both sides of the gate separation layer,
wherein channel posts among the plurality of channel posts adjacent to the slit structure have different curvatures in a planar view.

### Claim 3 (depends on 1)

The method of claim 1, wherein the curvature of the first curved portion is greater than the curvature of the second curved portion,
wherein the channel posts adjacent to the gate separation layer is formed to face the second curved portions of the channel posts to the gate separation layer, and
wherein plane structures of the channel posts adjacent to the gate separation layer includes a simple closed curve.

### Claim 4 (depends on 1)

The method of claim 1, wherein each of the channel posts adjacent to the gate separation layer is formed to include a first sector and a second sector base on a point, and
the first sector has a central angle different from a central angle of the second sector.

### Claim 5 (depends on 4)

The method of claim 4, wherein a first distance between the point of a chord of the first sector and the point of the first sector is shorter than a second distance between the point of a chord of the second sector.

### Claim 6 (depends on 1)

The method of claim 1, wherein forming the gate separation layer comprises:
selectively etching a selected portion of the stack structure to form a trench; and
forming a separating insulation layer in the trench,
wherein the selected portion of the stack structure comprises at least the uppermost sacrificial layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming the channel posts through the stack structure comprises providing the channel posts adjacent to the gate separation layer with a sidewall spaced apart from the gate separation layer.

### Claim 8 (depends on 1)

The method of claim 1, wherein forming the channel posts through the stack structure comprises providing the channel posts adjacent to the gate separation layer with a sidewall configured to make contact with the gate separation layer.

### Claim 9 (depends on 1)

The method of claim 1, wherein forming the gate separation layer comprises:
selectively etching an uppermost insulating interlayer in the stack structure to form a first trench;
forming a spacer on a sidewall of the first trench;
etching the stack structure using the spacer as an etch barrier to form a second trench extended from a bottom surface of the first trench and having a width narrower than a width of the first trench to separate the uppermost gate conductive layer; and
filling the first trench and the second trench with a separating insulation layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein forming the channel posts through the stack structure comprises providing the channel posts adjacent to the gate separation layer with a sidewall configured to make contact with the sidewall of the first trench and spaced apart from a sidewall of the second trench.