# US 12,225,727 B2 · United states 3D memory semiconductor devices and structures with memory cells

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- Number: US 12,225,727 B2
- Document ID: US12225727B2
- Status: Granted
- Kind: B2
- Application number: 18/738,967
- Filed: 2024-06-10
- Published: 2024-10-03
- Granted: 2025-02-11
- Earliest claimed: 2019-04-08
- Assignees: Monolithic 3D Inc.
- Applicants: Monolithic 3D Inc.
- Inventors: Zvi Or-Bach; Jin-Woo Han; Eli Lusky
- Web page: https://patentgrep.com/patent/US12225727B2

## CPC

- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- G11C 7/04: with means for avoiding disturbances due to temperature effects
- G11C 7/065: {Differential amplifiers of latching type}
- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/24: Bit-line control circuits
- G11C 16/28: using differential sensing or reference cells, e.g. dummy cells
- H10B 41/10: characterised by the top-view layout
- H10B 41/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/40: characterised by the peripheral circuit region
- H10B 43/10: characterised by the top-view layout
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 43/40: characterised by the peripheral circuit region
- H10B 51/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 80/00: Assemblies of multiple devices comprising at least one memory device covered by this subclass
- H10W 72/90: Bond pads, in general
- H10W 90/00: Package configurations
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 7/18: Bit line organisation; Bit line lay-out
- G11C 16/10: Programming or data input circuits
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C 16/16: for erasing blocks, e.g. arrays, words, groups
- H10W 90/792: {between multiple chips}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A 3D memory device including: a first structure including a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel, where the memory cell includes at least one charge trap structure, and where the at least one memory transistor is self-aligned to an overlaying another the at least one memory transistor, both being processed following a same lithography step; and a control level including a memory controller circuit, where the control level includes a plurality of latch sense amplifiers, where the control level is bonded to the first structure, and where the bonded includes hybrid bonding.

## Claims

### Claim 1

A 3D memory device, the device comprising:
a first structure comprising a plurality of memory cells,
wherein each memory cell of said plurality of memory cells comprises at least one memory transistor,
wherein each of said at least one memory transistor comprises a source, a drain, and a channel,
wherein said memory cell comprises at least one charge trap structure, and
wherein said at least one memory transistor is self-aligned to an overlaying another said at least one memory transistor, both being processed following a same lithography step; and
a control level comprising a memory controller circuit,
wherein said control level comprises a plurality of latch sense amplifiers,
wherein said memory controller circuit comprises a configuration to perform a self-differential read cycle,
wherein said control level is bonded to said first structure, and
wherein said bonded comprises hybrid bonding.

### Claim 2 (depends on 1)

The device according to claim 1,
wherein said channel comprises polysilicon,
wherein said source and/or said drain comprises metal atoms, and
wherein said metal atoms enable hot electron programming of said charge trap memory.

### Claim 3 (depends on 1)

The device according to claim 1, further comprising:
a bottom level comprising a first crystallized silicon layer; and
a top level comprising a second crystallized silicon layer,
wherein said bottom level is overlaid by said first structure, and
wherein said first structure is overlaid by said top level.

### Claim 4 (depends on 1)

The device according to claim 1,
wherein said control level comprises a plurality of temperature sensors.

### Claim 5 (depends on 1)

The device according to claim 1, wherein at least one of said channel comprises recrystallized material.

### Claim 6 (depends on 1)

The device according to claim 1,
wherein said memory controller circuit comprises a row buffer.

### Claim 7

A 3D memory device, the device comprising:
a first structure comprising a plurality of memory cells,
wherein each memory cell of said plurality of memory cells comprises at least one memory transistor,
wherein each of said at least one memory transistor comprises a source, a drain, and a channel;
a plurality of memory-line pillars,
wherein said plurality of memory-line pillars are vertically oriented, and
wherein said at least one memory transistor is self-aligned to an overlaying another said at least one memory transistor, both being processed following a same lithography step; and
a control level comprising a memory controller circuit,
wherein said memory controller circuit comprises plurality of a row buffers,
wherein said memory controller circuit comprises a configuration to perform a self-differential read cycle,
wherein said control level is bonded to said first structure, and
wherein said bonded comprises hybrid bonding.

### Claim 8 (depends on 7)

The device according to claim 7,
wherein each memory cell of said plurality of memory cells comprises a charge trap memory,
wherein said channel comprises polysilicon,
wherein said channel is horizontally oriented,
wherein said source and/or said drain comprises metal atoms, and
wherein said metal atoms enable hot electron programming of said charge trap memory.

### Claim 9 (depends on 7)

The device according to claim 7,
wherein each of said at least one memory transistor is directly connected to at least one of said plurality of memory-line pillars.

### Claim 10 (depends on 7)

The device according to claim 7,
wherein at least one of said plurality of memory cells comprises a tunneling oxide thinner than 1 nm.

### Claim 11 (depends on 7)

The device according to claim 7,
wherein said plurality of memory cells comprise a partially or fully metalized source, and/or, a partially or fully metalized drain.

### Claim 12

A 3D memory device, the device comprising:
a first structure comprising a plurality of memory cells,
wherein each memory cell of said plurality of memory cells comprises at least one memory transistor,
wherein each of said at least one memory transistor comprises a source, a drain, and a channel;
a plurality of memory-line pillars,
wherein said plurality of memory-line pillars are vertically oriented, and
wherein said at least one memory transistor is self-aligned to an overlaying another said at least one memory transistor, both being processed following a same lithography step; and
a control level comprising a memory controller circuit,
wherein said channel comprises recrystallized polysilicon,
wherein said memory controller circuit comprises a configuration to perform a self-differential read cycle,
wherein said control level is bonded to said first structure, and
wherein said bonded comprises hybrid bonding.

### Claim 13 (depends on 12)

The device according to claim 12,
wherein each memory cell of said plurality of memory cells comprises a charge trap memory,
wherein said channel comprises polysilicon,
wherein said channel is horizontally oriented,
wherein said source and/or said drain comprises metal atoms, and
wherein said metal atoms enable hot electron programming of said charge trap memory.

### Claim 14 (depends on 12)

The device according to claim 12,
wherein said memory controller circuit comprises a plurality of current sense amplifiers.

### Claim 15 (depends on 12)

The device according to claim 12,
wherein said memory controller circuit comprises a row buffer.

### Claim 16 (depends on 12)

The device according to claim 12,
wherein said plurality of memory cells comprise a partially or fully metalized source, and/or, a partially or fully metalized drain.

### Claim 17

A 3D memory device, the device comprising:
a first structure comprising a plurality of memory cells,
wherein each memory cell of said plurality of memory cells comprises at least one memory transistor,
wherein each of said at least one memory transistor comprises a source, a drain, and a channel;
a plurality of memory-line pillars,
wherein said plurality of memory-line pillars are vertically oriented, and
wherein said at least one memory transistor is self-aligned to an overlaying another said at least one memory transistor, both being processed following a same lithography step; and
a control level comprising a memory controller circuit,
wherein said memory controller circuit comprises plurality of a row buffers,
wherein said memory controller circuit comprises a calibration mode control circuit,
wherein said control level is bonded to said first structure, and
wherein said bonded comprises hybrid bonding.

### Claim 18 (depends on 17)

The device according to claim 17,
wherein said memory controller circuit comprises a row buffer.

### Claim 19 (depends on 17)

The device according to claim 17, further comprising:
a bottom level comprising a first crystallized silicon layer; and
a top level comprising a second crystallized silicon layer,
wherein said bottom level is overlaid by said first structure, and
wherein said first structure is overlaid by said top level.

### Claim 20 (depends on 17)

The device according to claim 17,
wherein said control level comprises a plurality of temperature sensors.