# US 12,225,725 B2 · Semiconductor devices and manufacturing methods of the same

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- Number: US 12,225,725 B2
- Document ID: US12225725B2
- Status: Granted
- Kind: B2
- Application number: 17/650,700
- Filed: 2022-02-11
- Published: 2022-05-26
- Granted: 2025-02-11
- Earliest claimed: 2018-06-11
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: So Hyeon Lee
- Web page: https://patentgrep.com/patent/US12225725B2

## CPC

- H10B 43/10: characterised by the top-view layout
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/30: characterised by the memory core region
- H10B 43/30: characterised by the memory core region
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- H10D 30/694: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H10B 43/40: characterised by the peripheral circuit region
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/683: {programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/037: {comprising charge-trapping insulators}
- H10P 14/27: {using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 30/40: into insulating materials
- H10P 50/283: {by chemical means}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/076: {in via holes or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a vertical stack of gate electrodes. The gate electrodes extend in different lengths to provide contact regions. The gate electrodes have a conductive region and an insulating region. Contact plugs fills contact holes that pass through the stack of gate electrodes in the contact regions. The contact plugs are connected to the gate electrodes. The contact plugs pass through a conductive region of one gate electrode and are electrically connected to the one gate electrode and pass through the insulating region of other gate electrodes in the contact region. The insulating region is disposed outside of the contact holes in a region in which the gate electrodes intersect the contact plugs.

## Claims

### Claim 1

A semiconductor device, comprising:
a plurality of gate conductive regions spaced apart from each other and stacked in a direction perpendicular to an upper surface of a substrate, the plurality of gate conductive regions including a first gate conductive region and a plurality of second gate conductive regions;
a plurality of gate insulating regions, each surrounded at least partially by each of the plurality of second gate conductive regions;
a contact plug filling a contact hole passing through the first gate conductive region and the plurality of gate insulating regions, and electrically connected to the first gate conductive region;
a first dielectric layer horizontally extended along the first gate conductive region, and covering an upper surface and a lower surface of the first gate conductive region; and
a plurality of second dielectric layers horizontally extended along the plurality of second gate conductive regions, and covering upper surfaces and lower surfaces of the plurality of second gate conductive regions,
wherein a distance from an adjacent edge of the first gate conductive region to the contact hole is different from a distance from an adjacent edge of each of the plurality of second gate conductive regions to the contact hole,
wherein a side surface of the contact plug has protruding portions protruding outwardly toward the plurality of gate conductive regions, and
wherein the plurality of second dielectric layers cover side surfaces of the plurality of second gate conductive regions facing the contact plug, and the first dielectric layer exposes a side surface of the first gate conductive region facing the contact plug.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the protruding portions contact the first gate conductive region and the plurality of gate insulating regions.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the contact plug further contacts the first dielectric layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein each of the protruding portions protrudes in a form of a band along the side surface of the contact plug.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the first dielectric layer and the plurality of second dielectric layers have a first thickness, and the protruding portions protrude by a first length, which is equal to or greater than the first thickness.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein an uppermost protruding portion among the protruding portions protrudes by a first length, and other protruding portions below the uppermost protruding portion among the protruding portions protrude by a second length, which is greater than the first length.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein each of the plurality of gate insulating regions occupies substantially a same level as each of the plurality of second gate conductive regions.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the plurality of gate insulating regions are arranged in a single row along the contact plug, in the direction perpendicular to the substrate.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the adjacent edge of the first gate conductive region is in contact with the contact plug and the adjacent edge of each of the plurality of second gate conductive regions is spaced apart from the contact plug.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein each of the plurality of gate insulating regions is disposed outside of the contact hole in a region in which the plurality of gate conductive regions intersect the contact plug.

### Claim 11

A semiconductor device, comprising:
a substrate arranged primarily in a horizontal direction, in a cross-sectional view, having a first region and a second region following the first region in the horizontal direction;
a plurality of gate conductive regions spaced apart from each other and stacked in a vertical direction perpendicular to the horizontal direction, the plurality of gate conductive regions including a first gate conductive region and a plurality of second gate conductive regions;
a plurality of gate insulating regions, each surrounded in the horizontal direction by each of the plurality of second gate conductive regions, each of the plurality of gate conductive regions being disposed within a horizontal plane of a single corresponding gate insulating region of the plurality of gate insulating regions;
a plurality of channels disposed in the first region of the substrate, passing through the plurality of gate conductive regions, and each including a channel region having an annular form; and
a contact plug disposed in the second region of the substrate, filling a contact hole passing through the first gate conductive region and the plurality of gate insulating regions, and electrically connected to the first gate conductive region,
wherein a side surface of the contact plug has protruding portions protruding outwardly in the horizontal direction toward the plurality of second gate conductive regions, and
wherein the semiconductor device further comprises:
a first dielectric layer horizontally extended along the first gate conductive region and covering an upper surface and a lower surface of the first gate conductive region; and
a plurality of second dielectric layers horizontally extended along the plurality of second gate conductive regions and covering upper surfaces and lower surfaces of the plurality of second gate conductive regions.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the plurality of second dielectric layers cover side surfaces of the plurality of second gate conductive regions facing the contact plug, and the first dielectric layer exposes a side surface of the first gate conductive region facing the contact plug.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, wherein the side surface of the contact plug further has an uppermost protruding portion protruding outwardly toward the first gate conductive region.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the protruding portions contact the plurality of gate insulating regions, and the uppermost protruding portion contacts the first gate conductive region.

### Claim 15 (depends on 11)

The semiconductor device of claim 11, wherein the plurality of gate insulating regions are vertically spaced apart from each other.

### Claim 16 (depends on 11)

The semiconductor device of claim 11, further comprising:
a substrate insulating layer disposed between the contact plug and the substrate.

### Claim 17

A semiconductor device, comprising:
a substrate having a first region and a second region;
a plurality of gate conductive regions spaced apart from each other and stacked in a direction perpendicular to an upper surface of the substrate, the plurality of gate conductive regions including a first gate conductive region and a plurality of second gate conductive regions;
a plurality of gate insulating regions, each surrounded at least partially by each of the plurality of second gate conductive regions;
a plurality of channels disposed in the first region of the substrate, passing through the plurality of gate conductive regions, and each including a channel region having an annular form;
a contact plug disposed in the second region of the substrate, filling a contact hole passing through the first gate conductive region and the plurality of gate insulating regions, and electrically connected to the first gate conductive region;
a first dielectric layer horizontally extended along the first gate conductive region and covering an upper surface and a lower surface of the first gate conductive region; and
a plurality of second dielectric layers horizontally extended along the plurality of second gate conductive regions and covering upper surfaces and lower surfaces of the plurality of second gate conductive regions,
wherein the plurality of second dielectric layers cover side surfaces of the plurality of second gate conductive regions facing the contact plug, and the first dielectric layer exposes a side surface of the first gate conductive region facing the contact plug.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein a side surface of the contact plug has protruding portions protruding outwardly toward the plurality of gate conductive regions.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, wherein a distance from an adjacent edge of the first gate conductive region to the contact hole is different from a distance from an adjacent edge of each of the plurality of second gate conductive regions to the contact hole.