# US 12,225,721 B2 · Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells

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- Number: US 12,225,721 B2
- Document ID: US12225721B2
- Status: Granted
- Kind: B2
- Application number: 17/841,925
- Filed: 2022-06-16
- Published: 2022-09-29
- Granted: 2025-02-11
- Earliest claimed: 2020-06-05
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: John D. Hopkins; Nancy M. Lomeli
- Web page: https://patentgrep.com/patent/US12225721B2

## CPC

- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/10: characterised by the top-view layout
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 43/10: characterised by the top-view layout
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A stack comprising vertically-alternating first tiers and second tiers is formed above the conductor tier. The stack comprises laterally-spaced memory-block regions. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from material of the second tiers. Spaced insulator-material bodies are formed in and longitudinally-along opposing sides of individual of the memory-block regions in a lowest of the first tiers. After forming the spaced insulator-material bodies, conductive material is formed in the lowest first tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.

## Claims

### Claim 1

A memory array comprising strings of memory cells, comprising:
a conductor tier comprising conductor material;
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above the conductor tier, channel-material strings of memory cells extending through the insulative tiers and the conductive tiers;
insulator-material bodies in and longitudinally-along opposing sides of individual of the memory blocks in a lowest of the conductive tiers, the insulator-material bodies being spaced relative one another longitudinally-along the memory blocks; and
conductive material in the lowest conductive tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier.

### Claim 2 (depends on 1)

The memory array of claim 1 wherein the insulator-material bodies comprise an oxide.

### Claim 3 (depends on 1)

The memory array of claim 1 wherein the conductive material is directly against the insulator-material bodies.

### Claim 4 (depends on 1)

The memory array of claim 1 wherein the insulator-material bodies do not laterally project into space between immediately-adjacent of the laterally-spaced memory block.

### Claim 5 (depends on 4)

The memory array of claim 4 wherein the conductive material completely horizontally surrounds individual peripheries of the insulator-material bodies.

### Claim 6 (depends on 5)

The memory array of claim 5 wherein the conductive material is directly against the insulator-material bodies.

### Claim 7 (depends on 1)

The memory array of claim 1 wherein the conductive material does not completely horizontally surround individual peripheries of the insulator-material bodies.

### Claim 8 (depends on 7)

The memory array of claim 7 wherein the conductive material horizontally covers a majority of the individual peripheries.

### Claim 9 (depends on 8)

The memory array of claim 8 wherein the conductive material horizontally covers at least 75% of the individual peripheries.

### Claim 10 (depends on 9)

The memory array of claim 9 wherein the conductive material is directly against the insulator-material bodies.

### Claim 11 (depends on 7)

The memory array of claim 7 wherein the insulator-material bodies individually span completely across space between immediately-adjacent of the laterally-spaced memory-block regions in a finished circuitry construction.

### Claim 12 (depends on 1)

The memory array of claim 1 wherein the lowest conductive tier is thicker than the conductive tiers there-above.

### Claim 13 (depends on 1)

The memory array of claim 1 wherein a lowest surface of the channel material of the channel-material strings is not directly against any of the conductor material of the conductor tier.

### Claim 14 (depends on 1)

The memory array of claim 1 wherein the conductive material in the lowest conductive tier is directly against a sidewall of the channel material of the channel-material strings.

### Claim 15 (depends on 1)

The memory array of claim 1 wherein the conductive material in the lowest conductive tier is directly against an uppermost surface of the conductor material of the conductor tier.