# US 12,225,715 B2 · Semiconductor device having semiconductor layers disposed between upper portions of the isolation structures and the active regions

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- Number: US 12,225,715 B2
- Document ID: US12225715B2
- Status: Granted
- Kind: B2
- Application number: 17/983,402
- Filed: 2022-11-09
- Published: 2024-02-15
- Granted: 2025-02-11
- Earliest claimed: 2022-08-12
- Assignees: Fujian Jinhua Integrated Circuit Co., Ltd.
- Applicants: Fujian Jinhua Integrated Circuit Co., Ltd.
- Inventors: Yu-Cheng Tung; Janbo Zhang
- Web page: https://patentgrep.com/patent/US12225715B2

## CPC

- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/482: {Bit lines}
- H10B 12/485: {Bit line contacts}
- H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug}
- H10B 12/488: {Word lines}
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device includes a substrate, a plurality of active regions disposed in the substrate and respectively extending along a first direction and arranged into an array, and a plurality of isolation structures disposed in the substrate between the active regions. The isolation structures respectively comprise an upper portion and a lower portion, wherein a sidewall of the upper portion comprises a first slope, a sidewall of the lower portion comprises a second slop, and the first slope and the second slope are different. The semiconductor device further includes a plurality of semiconductor layers disposed between the upper portions of the isolation structures and the active regions.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a plurality of active regions disposed in the substrate, respectively extending along a first direction and arranged into an array;
a plurality of isolation structures disposed in the substrate between the active regions and respectively comprising an upper portion having a first thickness and a lower portion having a second thickness, wherein a sidewall of the upper portion comprises a first slope, a sidewall of the lower portion comprises a second slop, and the first slope and the second slope are different; and
a plurality of semiconductor layers disposed between the upper portions of the isolation structures and the active regions.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the substrate comprises silicon, the semiconductor layers comprises silicon, germanium, or silicon germanium.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein bottom ends of the semiconductor layers are flush with boundaries between the upper portions and the lower portions of the isolation structures.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the second thickness is larger than the first thickness.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein top ends of the semiconductor layers are not coplanar.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, further comprising voids formed in the lower portions of the isolation structures.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a plurality of word lines disposed in the substrate, extending parallel along a second direction and cutting through the isolation structures and the active regions to divide each of the active regions into a center portion and two terminal portions;
a plurality of bit lines disposed on the substrate, extending parallel along a third direction and directly contacting the center portions of the active regions and the semiconductor layers at two sides of the center portions, wherein the first direction, the second direction, and the third direction are different directions, and the second direction and the third direction are perpendicular; and
a plurality of contact plugs disposed on the substrate and between the bit lines and directly contacting the terminal portions of the active regions.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, wherein the contact plugs are in direct contact with the semiconductor layers at one side of each of the terminal portions.

### Claim 9 (depends on 7)

The semiconductor device according to claim 7, wherein bottom ends of the isolation structures between the terminal portions are lower than bottom ends of the isolation structures at two sides of the center portions.

### Claim 10 (depends on 7)

The semiconductor device according to claim 7, wherein bottom ends of the semiconductor layers are lower than bottom surfaces of the contact plugs.

### Claim 11 (depends on 7)

The semiconductor device according to claim 7, wherein the word lines respectively comprise:
a conductive layer; and
an insulating capping layer disposed on the conductive layer, wherein top ends of the semiconductor layers are flush with top surfaces of the insulating capping layers, and bottom ends of the semiconductor layers are lower than bottom surfaces of the insulating capping layers.