# US 12,225,711 B2 · Semiconductor device comprising wiring layer over driver circuit

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- Number: US 12,225,711 B2
- Document ID: US12225711B2
- Status: Granted
- Kind: B2
- Application number: 18/382,551
- Filed: 2023-10-23
- Published: 2024-02-08
- Granted: 2025-02-11
- Earliest claimed: 2011-01-14
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Shunpei Yamazaki; Yasuhiko Takemura
- Web page: https://patentgrep.com/patent/US12225711B2

## CPC

- H10B 12/31: {having a storage electrode stacked over the transistor}
- G11C 5/10: for interconnecting capacitors
- G11C 11/401: forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge}
- H10B 12/05: {Making the transistor}
- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10B 12/48: {Data lines or contacts therefor}
- H10B 12/50: {Peripheral circuit region structures}
- H10D 1/042: {using deposition processes to form electrode extensions}
- H10D 1/716: {having vertical extensions}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 86/01: Manufacture or treatment
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10W 20/43: Layouts of interconnections
- H10W 20/4421: {the principal metal being copper}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.

## Claims

### Claim 1

A semiconductor device comprising:
a first layer comprising a transistor;
a second layer provided over the first layer, the second layer comprising a wiring layer; and
a third layer provided over the second layer, the third layer comprising an insulating layer,
wherein a first conductive layer is provided over the first layer,
wherein part of a side surface of the first conductive layer is in contact with the second layer,
wherein a second conductive layer is provided in a first opening provided in the second layer and in a second opening provided in the third layer,
wherein a third conductive layer is provided over the second conductive layer,
wherein the second conductive layer has a region in contact with a top surface of the first conductive layer and a region in contact with the side surface of the first conductive layer,
wherein, in a cross-sectional view, the second conductive layer has a first region overlapping with the first conductive layer, a second region, and a third region,
wherein, in the cross-sectional view, the second region and the third region do not overlap with the first conductive layer and sandwich the first region,
wherein, in a plan view, the second conductive layer has a region extending from the first region along one direction, and
wherein the third conductive layer has a region in contact with a top surface of the region extending from the first region.

### Claim 2

A semiconductor device comprising:
a first insulating layer;
a second insulating layer provided over the first insulating layer; and
a third insulating layer provided over the second insulating layer,
wherein a first conductive layer electrically connected to a transistor is provided over the first insulating layer,
wherein part of a side surface of the first conductive layer is in contact with the second insulating layer,
wherein a second conductive layer is provided in a first opening provided in the second insulating layer and in a second opening provided in the third insulating layer,
wherein a third conductive layer is provided over the second conductive layer,
wherein the second conductive layer has a region in contact with a top surface of the first conductive layer and a region in contact with the side surface of the first conductive layer,
wherein, in a cross-sectional view, the second conductive layer has a first region overlapping with the first conductive layer, a second region, and a third region,
wherein, in the cross-sectional view, the second region and the third region do not overlap with the first conductive layer and sandwich the first region,
wherein, in a plan view, the second conductive layer has a region extending from the first region along one direction,
wherein the third conductive layer has a region in contact with a top surface of the region extending from the first region, and
wherein the first opening and the second opening overlap each other.

### Claim 3

A semiconductor device comprising:
a first layer comprising a semiconductor substrate;
a second layer provided over the first layer, the second layer comprising a wiring layer; and
a third layer provided over the second layer, the third layer comprising an insulating layer,
wherein a first conductive layer is provided over the first layer,
wherein part of a side surface of the first conductive layer is in contact with the second layer,
wherein a second conductive layer is provided in a first opening provided in the second layer and in a second opening provided in the third layer,
wherein a third conductive layer is provided over the second conductive layer,
wherein the second conductive layer has a region in contact with a top surface of the first conductive layer and a region in contact with the side surface of the first conductive layer,
wherein, in a cross-sectional view, the second conductive layer has a first region overlapping with the first conductive layer, a second region, and a third region,
wherein, in the cross-sectional view, the second region and the third region do not overlap with the first conductive layer and sandwich the first region,
wherein, in a plan view, the second conductive layer has a region extending from the first region along one direction,
wherein the third conductive layer has a region in contact with a top surface of the region extending from the first region, and
wherein a transistor is provided below the first layer.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein only the part of the side surface of the first conductive layer is in contact with the second layer.

### Claim 5 (depends on 2)

The semiconductor device according to claim 2, wherein only the part of the side surface of the first conductive layer is in contact with the second insulating layer.

### Claim 6 (depends on 3)

The semiconductor device according to claim 3, wherein only the part of the side surface of the first conductive layer is in contact with the second layer.