# US 12,225,710 B2 · Memory device with cross shape active layer surrounded by word line

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- Number: US 12,225,710 B2
- Document ID: US12225710B2
- Status: Granted
- Kind: B2
- Application number: 18/524,646
- Filed: 2023-11-30
- Published: 2024-03-21
- Granted: 2025-02-11
- Earliest claimed: 2020-07-01
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Il Do Kim; Dong Sun Sheen; Seung Hwan Kim
- Web page: https://patentgrep.com/patent/US12225710B2

## CPC

- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10B 12/03: {Making the capacitor or connections thereto}
- H10B 12/05: {Making the transistor}
- H10B 12/482: {Bit lines}
- H10B 12/488: {Word lines}
- H10B 12/50: {Peripheral circuit region structures}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 48/362: {Unipolar transistors having ohmic electrodes on emitter-like, base-like, and collector-like regions, e.g. hot electron transistors [HET], metal base transistors [MBT], resonant tunnelling transistors [RTT], bulk barrier transistors [BBT], planar doped barrier transistors [PDBT] or charge injection transistors [CHINT]}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/80: characterised by the materials
- H10D 62/883: {Transition metal dichalcogenides, e.g. MoSe2}
- H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10D 86/60: wherein the TFTs are in active matrices
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/481: {FETs having two-dimensional material channels, e.g. transition metal dichalcogenide [TMD] FETs}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A memory device includes a substrate, an active layer spaced apart from a surface of the substrate and laterally oriented in a first direction and including an opened first side, a closed second side, and a channel layer between the first side and the second side, and a word line laterally oriented in a second direction crossing the first direction while surrounding the channel layer.

## Claims

### Claim 1

A memory device, comprising:
a substrate;
a cross shape active layer spaced apart from a surface of the substrate and laterally oriented in a first direction, and including a first side, a second side, and a channel layer between the first side and the second side; and
a word line laterally oriented in a second direction crossing the first direction while surrounding the channel layer.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the cross shape active layer is configured as a laterally oriented cylinder shape with an inner gap.

### Claim 3 (depends on 2)

The memory device of claim 2, further comprising a gap-fill material filling the inner gap.

### Claim 4 (depends on 3)

The memory device of claim 3, wherein the cross shape active layer includes:
a first source/drain region surrounding an end of one side of the gap-fill material; and
a second source/drain region surrounding an end of another end of the gap-fill material.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein the cross shape active layer includes a silicon layer, InGaZnOx, InSnZnOx, ZnSnOx, MoS2, WS2 or MoSe2.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the word line includes:
a surrounding portion surrounding the channel layer; and
extended portions extending in the second direction from both sides of the surrounding portion.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the word line includes:
an upper level portion positioned at a higher level than the channel layer;
a lower level portion positioned at a lower level than the channel layer; and
an intermediate level connection positioned between the upper level portion and the lower level portion while being positioned at the same level as the channel layer.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein the channel layer has a cross-type.

### Claim 9 (depends on 1)

The memory device of claim 1, further comprising:
a bit line coupled to the first side of the cross shape active layer and vertically oriented with respect to the substrate; and
a capacitor coupled to the second side of the cross shape active layer.

### Claim 10 (depends on 1)

The memory device of claim 1, wherein the substrate including a peripheral circuit portion.