# US 12,225,705 B2 · Memory device having error detection function, semiconductor device, and electronic device

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- Number: US 12,225,705 B2
- Document ID: US12225705B2
- Status: Granted
- Kind: B2
- Application number: 17/419,745
- Filed: 2020-02-11
- Published: 2022-03-17
- Granted: 2025-02-11
- Earliest claimed: 2019-02-22
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Hitoshi Kunitake; Tatsuya Onuki; Tomoaki Atsumi; Kiyoshi Kato
- Web page: https://patentgrep.com/patent/US12225705B2

## CPC

- H10B 12/00: Dynamic random access memory [DRAM] devices
- G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)}
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 29/12015: {comprising clock generation or timing circuitry}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines
- G11C 2029/0403: {during or with feedback to manufacture}
- G11C 2029/0411: {Online error correction}
- H10B 41/70: the floating gate being an electrode shared by two or more components
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10B: ELECTRONIC MEMORY DEVICES
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A memory device having an error detection function and being capable of storing a large amount of data per unit area is provided. A driver circuit of the memory device is formed using a transistor formed on a semiconductor substrate, and a memory cell of the memory device is formed using a thin film transistor. A plurality of layers each of which includes a memory cell using the thin film transistor can be stacked over the semiconductor substrate, so that the amount of data that can be stored per unit area can be increased. Part of a peripheral circuit including the memory device can be formed using a thin film transistor, and thus, an error detection circuit is formed using the thin film transistor and stacked over the semiconductor substrate.

## Claims

### Claim 1

A memory device comprising:
a first element layer comprising a memory cell;
a second element layer comprising an error detection circuit;
a semiconductor substrate comprising a driver circuit; and
a sense amplifier and a precharge circuit,
wherein the second element layer is positioned between the semiconductor substrate and the first element layer,
wherein the memory cell comprises a first transistor,
wherein the error detection circuit comprises a second transistor,
wherein the driver circuit comprises a third transistor,
wherein the sense amplifier comprises a fourth transistor,
wherein the precharge circuit comprises a fifth transistor,
wherein the first transistor and the second transistor each comprise a metal oxide in a channel formation region,
wherein the third transistor comprises silicon in a channel formation region,
wherein the first transistor and the second transistor each comprise a front gate and a back gate,
wherein the second element layer further comprises a switch circuit,
wherein the switch circuit comprises a first switch,
wherein a bit line provided in a direction perpendicular to the semiconductor substrate is electrically connected to the fourth transistor and the fifth transistor via a sixth transistor, and
wherein an output signal of the error detection circuit is output to the driver circuit through the first switch of the switch circuit.

### Claim 2

A memory device comprising:
a plurality of first element layers;
a second element layer comprising an error detection circuit;
a semiconductor substrate comprising a driver circuit; and
a sense amplifier and a precharge circuit,
wherein the second element layer is positioned between the semiconductor substrate and the plurality of first element layers,
wherein the plurality of first element layers each comprise a memory cell,
wherein the plurality of first element layers are stacked over each other,
wherein the memory cell comprises a first transistor,
wherein the error detection circuit comprises a second transistor,
wherein the driver circuit comprises a third transistor,
wherein the sense amplifier comprises a fourth transistor,
wherein the precharge circuit comprises a fifth transistor,
wherein the first transistor and the second transistor each comprise a metal oxide in a channel formation region,
wherein the third transistor comprises silicon in a channel formation region,
wherein the first transistor and the second transistor each comprise a front gate and a back gate, and
wherein a bit line provided in a direction perpendicular to the semiconductor substrate is electrically connected to the fourth transistor and the fifth transistor via a sixth transistor.

### Claim 3

A memory device comprising:
first to N-th first element layers;
a second element layer comprising a switch circuit; and
a semiconductor substrate,
wherein a K-th first element layer of the first to N-th first element layers comprises a memory cell using a first transistor formed in the K-th first element layer,
wherein the second element layer comprises an error detection circuit using a second transistor formed in the second element layer,
wherein the semiconductor substrate comprises a driver circuit using a third transistor formed in the semiconductor substrate,
wherein the second element layer is stacked over the semiconductor substrate,
wherein the K-th first element layer of the first to N-th first-element layers is stacked over the second element layer,
wherein the K-th first element layer of the first to N-th first element layers is stacked over the (K−1)-th first element layer,
wherein N is a natural number greater than or equal to 2,
wherein K is an integer greater than or equal to 2 and less than or equal to N,
wherein the first transistor and the second transistor each comprise a metal oxide in a channel formation region,
wherein the first transistor and the second transistor each comprise a front gate and a back gate,
wherein the third transistor comprises silicon in a channel formation region,
wherein the switch circuit comprises a first switch and a second switch,
wherein the first switch of the switch circuit is electrically connected to a bit line via a fourth transistor, and
wherein the second switch of the switch circuit is electrically connected to the error detection circuit.