# US 12,225,704 B2 · 3D memory devices and structures with memory arrays and metal layers

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- Number: US 12,225,704 B2
- Document ID: US12225704B2
- Status: Granted
- Kind: B2
- Application number: 18/731,340
- Filed: 2024-06-02
- Published: 2024-09-26
- Granted: 2025-02-11
- Earliest claimed: 2016-12-30
- Assignees: Monolithic 3D Inc.
- Applicants: Monolithic 3D Inc.
- Inventors: Zvi Or-Bach; Jin-Woo Han; Brian Cronquist
- Web page: https://patentgrep.com/patent/US12225704B2

## CPC

- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- H10B 10/125: {the MOSFET being a thin film transistor [TFT]}
- G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells}
- G11C 11/5635: {Erasing circuits}
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 16/0416: {comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/10: Programming or data input circuits
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C 16/16: for erasing blocks, e.g. arrays, words, groups
- G11C 16/24: Bit-line control circuits
- G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written}
- G11C 29/1201: {comprising I/O circuitry}
- G11C 29/4401: {for self repair}
- G11C 29/76: {using address translation or modifications}
- G11C 29/783: {with refresh of replacement cells, e.g. in DRAMs}
- H10B 10/18: {Peripheral circuit regions}
- H10B 12/50: {Peripheral circuit region structures}
- H10B 41/10: characterised by the top-view layout
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10B 43/10: characterised by the top-view layout
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10B 51/10: characterised by the top-view layout
- H10B 51/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 80/00: Assemblies of multiple devices comprising at least one memory device covered by this subclass
- H10W 90/00: Package configurations
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 11/223: {using MOS with ferroelectric gate insulating film}
- G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines
- G11C 11/412: using field-effect transistors only
- G11C 29/70: {Masking faults in memories by using spares or by reconfiguring}
- G11C 2029/0403: {during or with feedback to manufacture}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 95/11: {Separation of active layers from substrates}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 46/301: {for alignment}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/792: {between multiple chips}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device including: a first level including at least four independently controlled first memory arrays, where the first level includes first transistors; a second level disposed on top of the first level, where the second level includes second memory arrays; and a third level disposed on top of the second level, where the third level includes third transistors and a plurality of third metal layers, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes, where the second filled holes are aligned to the first filled holes with a more than 1 nm but less than 40 nm alignment error, and where the third level includes at least one SRAM memory array.

## Claims

### Claim 1

A semiconductor device, the device comprising:
a first level comprising at least four independently controlled first memory arrays,
wherein said first level comprises a plurality of first transistors;
a second level disposed on top of said first level,
wherein said second level comprises a plurality of second memory arrays; and
a third level disposed on top of said second level,
wherein said third level comprises a plurality of third transistors and a plurality of third metal layers,
wherein said third level is bonded to said second level,
wherein said bonded comprises oxide to oxide bonding regions and a plurality of metal to metal bonding regions,
wherein said first level comprises first filled holes,
wherein said second level comprises second filled holes,
wherein said second filled holes are aligned to said first filled holes with a more than 1 nm but less than 40 nm alignment error, and
wherein said third level comprises at least one SRAM memory array.

### Claim 2 (depends on 1)

The device according to claim 1,
wherein said third level comprises at least one Look-Up-Table (“LUT”) circuit.

### Claim 3 (depends on 1)

The device according to claim 1, further comprising:
a plurality of redundancy memory cells.

### Claim 4 (depends on 1)

The device according to claim 1,
wherein said plurality of first memory arrays comprises a plurality of first DRAM (Dynamic Random Access Memory) cells, and
wherein said plurality of second memory arrays comprises a plurality of second DRAM (Dynamic Random Access Memory) cells.

### Claim 5 (depends on 1)

The device according to claim 1,
wherein said third level comprises control circuits providing control access to said plurality of first memory arrays, and
wherein said third level comprises control circuits providing control access to said plurality of second memory arrays.

### Claim 6 (depends on 1)

The device according to claim 1,
wherein said plurality of first memory arrays comprise at least four sub-arrays, and
wherein each of said at least four sub-arrays comprises independent control line access.

### Claim 7 (depends on 1)

The device according to claim 1,
wherein said plurality of first memory arrays comprises a plurality of NAND type memory.

### Claim 8

A semiconductor device, the device comprising:
a first level comprising at least four independently controlled first memory arrays;
a second level disposed on top of said first level,
wherein said second level comprises a plurality of second memory arrays;
a third level disposed on top of said second level,
wherein said third level comprises a plurality of third transistors and a plurality of third metal layers,
wherein said third level is bonded to said second level,
wherein said bonded comprises oxide to oxide bonding regions and a plurality of metal to metal bonding regions,
wherein said first level comprises first filled holes,
wherein said second level comprises second filled holes,
wherein said third level comprises a plurality of decoder circuits,
wherein said second filled holes are aligned to said first filled holes with a more than 1 nm but less than 40 nm alignment error, and
wherein said third level comprises circuits to perform a memory refresh.

### Claim 9 (depends on 8)

The device according to claim 8, further comprising:
a fourth level comprising crystalline silicon, said fourth level is disposed underneath said first level.

### Claim 10 (depends on 8)

The device according to claim 8, further comprising:
a plurality of redundancy memory cells.

### Claim 11 (depends on 8)

The device according to claim 8,
wherein at least one of said first transistors comprises a metal gate.

### Claim 12 (depends on 8)

The device according to claim 8,
wherein said third level comprises control circuits providing control access to said plurality of first memory arrays, and
wherein said third level comprises control circuits providing control access to said plurality of second memory arrays.

### Claim 13 (depends on 8)

The device according to claim 8,
wherein said plurality of first memory arrays comprise at least four sub-arrays, and
wherein each of said at least four sub-arrays comprises independent control line access.

### Claim 14 (depends on 8)

The device according to claim 8,
wherein said plurality of first memory arrays comprise a NAND type memory.

### Claim 15

A semiconductor device, the device comprising:
a first level comprising at least four independently controlled first memory arrays,
a second level disposed on top of said first level,
wherein said second level comprises a plurality of second memory arrays; and
a third level disposed on top of said second level,
wherein said third level comprises a plurality of third transistors and a plurality of third metal layers,
wherein said third level is bonded to said second level,
wherein said bonded comprises oxide to oxide bonding regions and a plurality of metal to metal bonding regions,
wherein said first level comprises first filled holes,
wherein said second level comprises second filled holes,
wherein said second filled holes are aligned to said first filled holes with a more than 1 nm but less than 40 nm alignment error, and
wherein said third level comprises redundancy and repair circuits.

### Claim 16 (depends on 15)

The device according to claim 15,
wherein singulation of said device comprises use of laser assisted dicing.

### Claim 17 (depends on 15)

The device according to claim 15,
wherein said third level comprises a plurality of decoder circuits, and
wherein said device comprises a plurality of conductive feed-through paths disposed through at least said second level.

### Claim 18 (depends on 15)

The device according to claim 15,
wherein said plurality of first memory arrays comprises a plurality of first DRAM (Dynamic Random Access Memory) cells, and
wherein said plurality of second memory arrays comprises a plurality of second DRAM (Dynamic Random Access Memory) cells.

### Claim 19 (depends on 15)

The device according to claim 15,
wherein said plurality of first memory arrays comprise at least four sub-arrays, and
wherein each of said at least four sub-arrays comprises independent control line access.

### Claim 20 (depends on 15)

The device according to claim 15,
wherein said plurality of first memory arrays comprise a NAND type memory.