# US 12,225,703 B2 · Methods of manufacturing a semiconductor device using a mask

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,225,703 B2
- Document ID: US12225703B2
- Status: Granted
- Kind: B2
- Application number: 18/479,323
- Filed: 2023-10-02
- Published: 2024-01-25
- Granted: 2025-02-11
- Earliest claimed: 2020-10-19
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Mingyu Kim; Munhyeon Kim; Daewon Ha
- Web page: https://patentgrep.com/patent/US12225703B2

## CPC

- H10B 10/12: {comprising a MOSFET load element}
- G11C 11/412: using field-effect transistors only
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A method of manufacturing a semiconductor device includes forming a first sacrificial and first active layer on a substrate; forming a first mask pattern on a portion of the substrate; etching the first sacrificial and first active layer partially using the first mask pattern to expose a portion of a top surface of the substrate; forming a semiconductor layer on the exposed top surface of the substrate; forming sacrificial layers and active layers on the first active and semiconductor layer, the active layers including an uppermost second active layer; forming a second mask pattern on a portion of the second active layer; forming a trench using the second mask pattern, the trench defining a first and second active pattern; and removing the sacrificial layers to form a first and second channel patterns on the first and second active patterns, respectively, wherein the first active pattern includes the semiconductor layer.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
forming a first sacrificial layer and a first active layer on a substrate;
forming a first mask pattern on a portion of the substrate;
etching the first sacrificial layer and the first active layer partially using the first mask pattern as a mask to expose a portion of a top surface of the substrate;
forming a semiconductor layer on the exposed portion of the top surface of the substrate;
forming sacrificial layers and active layers on the first active layer and the semiconductor layer, the active layers including an uppermost second active layer;
forming a second mask pattern on a portion of the uppermost second active layer;
forming a trench using the second mask pattern as an etch mask, the trench defining a first active pattern and a second active pattern; and
removing the sacrificial layers to form a first channel pattern and a second channel pattern on the first active pattern and the second active pattern, respectively,
wherein the first active pattern includes the semiconductor layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein:
the semiconductor layer is disposed below and apart from the first channel pattern.

### Claim 3 (depends on 1)

The method of claim 1, wherein:
a pair of adjacent first active patterns respectively constitute a pull-up transistor; and
a pair of adjacent second active patterns respectively constitute a pull-down transistor and a pass-gate transistor.

### Claim 4 (depends on 3)

The method of claim 3, wherein:
the second active pattern of the pass-gate transistor includes the semiconductor layer; and
the semiconductor layer of the pass-gate transistor comprises at least one of silicon or silicon boride.

### Claim 5 (depends on 1)

The method of the claim 1, wherein:
the first channel pattern and the second channel pattern respectively comprise a plurality of semiconductor patterns; and
there are more or less semiconductor patterns of the first channel pattern than semiconductor patterns of the second channel pattern.

### Claim 6 (depends on 1)

The method of the claim 1, wherein:
a lowermost semiconductor pattern of the second channel pattern is disposed at a lower level than a lowermost semiconductor pattern of the first channel pattern.

### Claim 7 (depends on 1)

The method of the claim 1, wherein forming the semiconductor layer includes:
performing an epitaxial growth process on the exposed portion of the top surface of the substrate.

### Claim 8 (depends on 1)

The method of the claim 1, wherein forming the semiconductor layer includes:
growing a silicon layer from the exposed portion of the top surface of the substrate; and
doping the silicon layer with impurities.

### Claim 9 (depends on 1)

The method of the claim 1, wherein:
a top surface of the semiconductor layer is coplanar with a top surface of the first active layer.

### Claim 10

A method of manufacturing a semiconductor device, the method comprising:
forming a first sacrificial layer and a first active layer on a substrate;
forming a first mask pattern on a portion of the substrate;
etching the first sacrificial layer and the first active layer partially using the first mask pattern as a mask to expose a portion of a top surface of the substrate;
forming a first semiconductor layer and a second semiconductor layer on the exposed portion of the top surface of the substrate;
forming staked sacrificial layers and active layers on the first active layer and the semiconductor layer, the active layers including an uppermost second active layer;
forming a second mask pattern on a portion of the uppermost second active layer;
forming a trench using the second mask pattern as an etch mask, the trench defining a first active pattern and a second active pattern; and
removing the sacrificial layers to form a first channel pattern and a second channel pattern on the first active pattern and the second active pattern, respectively,
wherein a top surface of the first semiconductor layer and a top surface of the second semiconductor layer are coplanar with a top surface of the first active layer,
wherein the first semiconductor layer is a portion of the first active pattern, and
wherein the second semiconductor layer is a portion of the second active pattern.

### Claim 11 (depends on 10)

The method of claim 10, wherein:
a pair of adjacent first active patterns respectively constitute a pull-up transistor; and
a pair of adjacent second active patterns respectively constitute a pull-down transistor and a pass-gate transistor.

### Claim 12 (depends on 10)

The method of claim 10, wherein:
the first semiconductor layer is disposed below and apart from the first channel pattern; and
the second semiconductor layer is disposed below and apart from the second channel pattern.

### Claim 13 (depends on 10)

The method of claim 10, wherein:
the first semiconductor layer comprises at least one of silicon or silicon phosphide; and
the second semiconductor layer comprises at least one of silicon or silicon boride.

### Claim 14 (depends on 10)

The method of the claim 10, wherein forming the first semiconductor layer and the second semiconductor layer includes:
performing an epitaxial growth process on the exposed portion of the top surface of the substrate.

### Claim 15 (depends on 10)

The method of the claim 10, wherein forming the first semiconductor layer and the second semiconductor layer includes:
growing a silicon layer from the exposed portion of the top surface of the substrate; and
doping the silicon layer with impurities.

### Claim 16

A method of manufacturing a semiconductor device, the method comprising:
forming a first active pattern and a second active pattern on a substrate;
forming a sacrificial pattern extending in a first direction on the first active pattern and the second active pattern, the first direction extending in parallel with an upper surface of the substrate;
etching the first active pattern and the second active pattern using the sacrificial pattern as a mask to form a first recess in the first active pattern and a second recess in the second active pattern, the first active pattern and the second active pattern respectively including semiconductor patterns exposed by the first recess and the second recess;
forming a first source/drain pattern in the first recess and a second source/drain pattern in the second recess;
removing the sacrificial pattern to expose a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern; and
sequentially forming a gate insulating layer and a gate electrode on the exposed the first, the second, and the third semiconductor patterns,
wherein the forming of the active patterns includes:
forming a first sacrificial layer and a first active layer on the substrate;
forming a first mask pattern on a portion of the substrate;
etching the first sacrificial layer and the first active layer partially using the first mask pattern as a mask to expose a portion of a top surface of the substrate;
forming a semiconductor layer on the exposed portion of the top surface of the substrate, wherein a top surface of the semiconductor layer is coplanar with a top surface of the first active layer;
forming staked sacrificial layers and active layers on the first active layer and the semiconductor layer, the active layers including an uppermost second active layer;
forming a second mask pattern on a portion of the uppermost second active layer; and
forming a trench using the second mask pattern as an etch mask, the trench defining the first active pattern and the second active pattern,
wherein the first active pattern comprises a semiconductor layer disposed below and apart from the first channel pattern, and
wherein the semiconductor layer comprises at least one of silicon or silicon phosphide.

### Claim 17 (depends on 16)

The method of claim 16, wherein:
a pair of adjacent first active patterns respectively constitute a pull-up transistor; and
a pair of adjacent second active patterns respectively constitute a pull-down transistor and a pass-gate transistor.

### Claim 18 (depends on 16)

The method of the claim 16, wherein:
there are more or less semiconductor patterns of the first active pattern than semiconductor patterns of the second active pattern.

### Claim 19 (depends on 16)

The method of the claim 16, wherein forming the semiconductor layer includes:
performing an epitaxial growth process on the exposed portion of the top surface of the substrate.

### Claim 20 (depends on 16)

The method of the claim 16, wherein forming the semiconductor layer includes:
growing a silicon layer from the exposed portion of the top surface of the substrate; and doping the silicon layer with impurities.