# US 12,225,658 B2 · Interlaced crosstalk controlled traces, vias, and capacitors > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,225,658 B2 - Document ID: US12225658B2 - Status: Granted - Kind: B2 - Application number: 18/357,440 - Filed: 2023-07-24 - Published: 2023-11-16 - Granted: 2025-02-11 - Earliest claimed: 2021-06-01 - Assignees: Cisco Technology, Inc. - Applicants: Cisco Technology, Inc. - Inventors: Shadi Ebrahimi Asl; Stephen Aubrey Scearce; Quinn Gaumer; Linda W. Scott - Web page: https://patentgrep.com/patent/US12225658B2 ## CPC - H05K 1/0218: {by printed shielding conductors, ground planes or power plane (H05K1/0236 takes precedence)} - H05K 1/0298: {Multilayer circuits} - H05K 1/115: {Via connections; Lands around holes or via connections (H05K1/112 takes precedence)} - H05K 1/181: associated with surface mounted components - H05K 3/0047: {Drilling of holes} - H05K 3/303: with surface mounted components (H05K3/32 takes precedence) - H05K 3/42: Plated through-holes {or plated via connections} - H05K 1/0219: {Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors} - H05K 1/0231: {Capacitors or dielectric substances} - H05K 1/0245: {Lay-out of balanced signal pairs, e.g. differential lines or twisted lines} - H05K 2201/10015: Non-printed capacitor - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ## Abstract A multilayer printed circuit board having a stackup including an upper half of the stackup and a lower half of the stackup, the multilayer printed circuit board having a top exposed surface and a bottom exposed surface, a first trace and via structure, having one portion disposed on the top exposed surface and another portion disposed within the upper half of the stackup, a second trace and via structure, having one portion disposed on the top exposed surface and another portion disposed within the upper half of the stackup, and first electrical components and second electrical components disposed on the top exposed surface of the multilayer printed circuit board and associated, respectively, with the first trace and via structure and the second trace and via structure, wherein the first electrical components are mounted orthogonally with respect to the second electrical components. ## Claims ### Claim 1 A method comprising: routing, on a first internal layer of a multilayer printed circuit board, a first pair of traces, electrically connected to first vias of a first trace and via structure, between second vias of a second trace and via structure; routing, on a second internal layer of the multilayer printed circuit board, a second pair of traces, electrically connected to the second vias of the second trace and via structure, between the first vias of the first trace and via structure; backdrilling the first vias of the first trace and via structure to a first depth; and backdrilling the second vias of the second trace and via structure to a second depth that is deeper than the first depth, wherein the first vias of the first trace and via structure are separated by a first distance and the second vias of the second trace and via structure are separated by a second distance that is less than the first distance. ### Claim 2 (depends on 1) The method of claim 1, further comprising: electrically connecting first capacitors to the first trace and via structure in a first direction on the multilayer printed circuit board; and electrically connecting second capacitors to the second trace and via structure in a second direction, orthogonal to the first direction, on the multilayer printed circuit board. ### Claim 3 (depends on 1) The method of claim 1, wherein the first vias of the first trace and via structure and the second vias of the second trace and via structure comprise one block of an array of blocks of intermingled differential vias in the multilayer printed circuit board. ### Claim 4 (depends on 3) The method of claim 3, further comprising positioning a first block in the array of blocks offset from a second block in the array of blocks. ### Claim 5 (depends on 3) The method of claim 3, wherein each block in the array of blocks of intermingled differential vias comprises two pairs of differential vias arranged in a square pattern, with each via of each pair of differential vias centered on a respective vertex of the square pattern. ### Claim 6 (depends on 5) The method of claim 5, further comprising arranging each block in the array of blocks of intermingled differential vias to have two pairs of differential vias arranged in a square pattern, with each via of each pair of differential vias centered on a respective vertex of the square pattern. ### Claim 7 (depends on 3) The method of claim 3, further comprising positioning ground vias that extend between a top exposed surface and a bottom exposed surface of the multilayer printed circuit board, the ground vias being spaced symmetrically around each block in the array of blocks of intermingled differential vias. ### Claim 8 (depends on 7) The method of claim 7, wherein the first vias of the first trace and via structure and the second vias of the second trace and via structure are signal vias and a signal via-to-ground via (S:G) ratio deployed in the multilayer printed circuit board has a value of up to 72:16. ### Claim 9 (depends on 1) The method of claim 1, wherein the first vias of the first trace and via structure have a first length and the second vias of the second trace and via structure have a second length shorter than the first length. ### Claim 10 (depends on 9) The method of claim 9, further comprising backdrilling third vias from a side of the multilayer printed circuit board opposite to a side of the multilayer printed circuit board from which the first vias of the first trace and via structure and the second vias of the second trace and via structure are backdrilled. ### Claim 11 A method comprising: routing, on a first internal layer in a multilayer printed circuit board, a first pair of traces, electrically connected to first vias of a first trace and via structure, between second vias of a second trace and via structure; routing, on a second internal layer in the multilayer printed circuit board, a second pair of traces, electrically connected to the second trace and via structure, between the first vias of the first trace and via structure; backdrilling the first vias of the first trace and via structure to a first depth; and backdrilling the second vias of the second trace and via structure to a second depth that is deeper than the first depth, wherein the first pair of traces and the second pair of traces run parallel to one another, and wherein the first vias of the first trace and via structure are separated by a first distance and the second vias of the second trace and via structure are separated by a second distance that is less than the first distance. ### Claim 12 (depends on 11) The method of claim 11, further comprising: electrically connecting first capacitors to the first trace and via structure in a first direction on the multilayer printed circuit board; and electrically connecting second capacitors to the second trace and via structure in a second direction, orthogonal to the first direction, on the multilayer printed circuit board. ### Claim 13 (depends on 11) The method of claim 11, wherein the first vias of the first trace and via structure and the second vias of the second trace and via structure comprise one block of an array of blocks of intermingled differential vias in the multilayer printed circuit board. ### Claim 14 (depends on 13) The method of claim 13, further comprising positioning a first block in the array of blocks offset from a second block in the array of blocks. ### Claim 15 (depends on 13) The method of claim 13, wherein each block in the array of blocks of intermingled differential vias comprises two pairs of differential vias arranged in a square pattern, with each via of each pair of differential vias centered on a respective vertex of the square pattern. ### Claim 16 (depends on 15) The method of claim 15, further comprising arranging each block in the array of intermingled differential vias to have two pairs of differential vias arranged in a square pattern, with each via of each pair of differential vias centered on a respective vertex of the square pattern. ### Claim 17 A method comprising: assembling a multilayer printed circuit board comprising a stackup of layers including an upper half of the stackup and a lower half of the stackup; routing in the upper half of the stackup, on a first internal layer of the multilayer printed circuit board, a first pair of traces, electrically connected to first vias of a first trace and via structure, between second vias of a second trace and via structure; routing in the upper half of the stackup, on a second internal layer of the multilayer printed circuit board, a second pair of traces, electrically connected to the second vias of the second trace and via structure, between the first vias of the first trace and via structure; backdrilling from the lower half of the stackup the first vias of the first trace and via structure to a first depth; and backdrilling from lower half the second vias of the second trace and via structure to a second depth that is deeper than the first depth, wherein the first vias of the first trace and via structure are separated by a first distance and the second vias of the second trace and via structure are separated by a second distance that is less than the first distance. ### Claim 18 (depends on 17) The method of claim 17, wherein the first vias of the first trace and via structure and the second vias of the second trace and via structure comprise one block of an array of blocks of intermingled differential vias and each block in the array of blocks of intermingled differential vias comprises two pairs of differential vias arranged in a square pattern, with each via of each pair of differential vias centered on a respective vertex of the square pattern. ### Claim 19 (depends on 18) The method of claim 18, further comprising arranging ground vias that extend between a top exposed surface and a bottom exposed surface of the multilayer printed circuit board, the ground vias being spaced symmetrically around each block in the array of blocks of intermingled differential vias. ### Claim 20 (depends on 17) The method of claim 17, wherein the first vias of the first trace and via structure have a first length and the second vias of the second trace and via structure have a second length shorter than the first length.