# US 12,225,306 B2 · Clock generation circuit and image sensor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,225,306 B2 - Document ID: US12225306B2 - Status: Granted - Kind: B2 - Application number: 17/959,264 - Filed: 2022-10-03 - Published: 2024-04-04 - Granted: 2025-02-11 - Earliest claimed: 2022-10-03 - Assignees: Pixart Imaging Inc. - Applicants: PixArt Imaging Inc. - Inventors: Poh Weng Yem - Web page: https://patentgrep.com/patent/US12225306B2 ## CPC - H04N 25/7795: {Circuitry for generating timing or clock signals} - H03K 3/0231: Astable circuits {(H03K3/0315 takes precedence)} - H04N 25/75: Circuitry for providing, modifying or processing image signals from the pixel array - H04N 25/772: comprising A/D, V/T, V/F, I/T or I/F converters - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A clock generation circuit, comprising a first RC circuit, a first switch, a second RC circuit, a second switch, a comparator and a logic circuit. The first RC circuit comprises a first capacitor, coupled to a first predetermined voltage level and a second predetermined voltage level. The second RC circuit comprises a second capacitor, coupled to the first switch. The comparator comprises: a first input terminal, coupled to the second RC circuit and the second switch; a second input terminal, configured to receive a reference voltage level; and an output terminal, coupled to a control terminal of the first switch and a control terminal of the second switch. The logic circuit is coupled to the output terminal of the comparator, configured to generate a clock signal. In one embodiment, the clock generation circuit is applied to an image sensor. ## Claims ### Claim 1 A clock generation circuit, comprising: a first RC circuit, comprising a first capacitor, coupled to a first predetermined voltage level and a second predetermined voltage level; a first switch, coupled to the first RC circuit; a second RC circuit, comprising a second capacitor, coupled to the first switch; a second switch, coupled to the second RC circuit; a comparator, comprising: a first input terminal, coupled to the second RC circuit and the second switch; a second input terminal, configured to receive a reference voltage level; and an output terminal, coupled to a control terminal of the first switch and a control terminal of the second switch; and a logic circuit, coupled to the output terminal of the comparator, configured to generate a clock signal; wherein the first switch and the second switch turn on and the second capacitor is discharged when a voltage of the second capacitor is higher than the reference voltage level; wherein the clock generation circuit further comprises: a discharging time setting circuit, configured to set a discharging time during which the second capacitor is discharged. ### Claim 2 (depends on 1) The clock generation circuit of claim 1, wherein the first RC circuit further comprises: a first resistor, coupled between the first predetermined voltage level and the first capacitor. ### Claim 3 (depends on 1) The clock generation circuit of claim 1, wherein the second RC circuit further comprises: a second resistor, coupled to the first switch, the second capacitor, the second switch and the first input terminal. ### Claim 4 (depends on 1) The clock generation circuit of claim 1, wherein the logic circuit is a D flip flop. ### Claim 5 (depends on 1) The clock generation circuit of claim 1, wherein the first RC circuit is provided outside an IC; wherein the first switch, the second RC circuit, the second switch, the comparator and the logic circuit are provided inside the IC. ### Claim 6 (depends on 1) The clock generation circuit of claim 1, wherein the first switch and the second switch turn off and the second capacitor is charged when a voltage of the second capacitor is lower than the reference voltage level. ### Claim 7 (depends on 1) The clock generation circuit of claim 1, wherein the discharging time setting circuit comprises: a third resistor, coupled between the first capacitor and the first switch; and a fourth resistor, coupled between the second capacitor and the second switch. ### Claim 8 (depends on 1) The clock generation circuit of claim 1, wherein the discharging time setting circuit comprises the first switch and the second switch, if the first switch and the second switch has adjustable resistances. ### Claim 9 An image sensor, comprises: a pixel array, configured to sense an image to generate image sensing signals; a reading circuit, configured to read the image sensing signals; an ADC, configured to generate digital signals according to the image sensing signals; and a clock generation circuit, comprising: a first RC circuit, comprising a first capacitor, coupled to a first predetermined voltage level and a second predetermined voltage level; a first switch, coupled to the first RC circuit; a second RC circuit, comprising a second capacitor, coupled to the first switch; a second switch, coupled to the second RC circuit; a comparator, comprising: a first input terminal, coupled to the second RC circuit and the second switch; a second input terminal, configured to receive a reference voltage level; and an output terminal, coupled to a control terminal of the first switch and a control terminal of the second switch; and a logic circuit, coupled to the output terminal of the comparator, configured to generate a clock signal to at least one of the pixel array, the reading circuit and the ADC; wherein the first switch and the second switch turn on and the second capacitor is discharged when a voltage of the second capacitor is higher than the reference voltage level; wherein the image sensor further comprises: a discharging time setting circuit, configured to set a discharging time during which the second capacitor is discharged. ### Claim 10 (depends on 9) The image sensor of claim 9, wherein the first RC circuit further comprises: a first resistor, coupled between the first predetermined voltage level and the first capacitor. ### Claim 11 (depends on 9) The image sensor of claim 9, wherein the second RC circuit further comprises: a second resistor, coupled to the first switch, the second capacitor, the second switch and the first input terminal. ### Claim 12 (depends on 9) The image sensor of claim 9, wherein the logic circuit is a D flip flop. ### Claim 13 (depends on 9) The image sensor of claim 9, wherein the first RC circuit is provided outside an IC; wherein the first switch, the second RC circuit, the second switch, the comparator and the logic circuit are provided inside the IC. ### Claim 14 (depends on 9) The image sensor of claim 9, wherein the first switch and the second switch turn off and the second capacitor is charged when a voltage of the second capacitor is lower than the reference voltage level. ### Claim 15 (depends on 9) The image sensor of claim 9, wherein the discharging time setting circuit comprises: a third resistor, coupled between the first capacitor and the first switch; and a fourth resistor, coupled between the second capacitor and the second switch. ### Claim 16 (depends on 9) The image sensor of claim 9, wherein the discharging time setting circuit comprises the first switch and the second switch, if the first switch and the second switch has adjustable resistances. ### Claim 17 A clock generation circuit, comprising: a first RC circuit, comprising a first capacitor, coupled to a first predetermined voltage level and a second predetermined voltage level; a first switch, coupled to the first RC circuit; a second RC circuit, comprising a second capacitor, coupled to the first switch; a second switch, coupled to the second RC circuit; a comparator, comprising: a first input terminal, coupled to the second RC circuit and the second switch; a second input terminal, configured to receive a reference voltage level; and an output terminal, coupled to a control terminal of the first switch and a control terminal of the second switch; and a logic circuit, coupled to the output terminal of the comparator, configured to generate a clock signal; wherein the first RC circuit is provided outside an IC; wherein the first switch, the second RC circuit, the second switch, the comparator and the logic circuit are provided inside the IC. ### Claim 18 An image sensor, comprises: a pixel array, configured to sense an image to generate image sensing signals; a reading circuit, configured to read the image sensing signals; an ADC, configured to generate digital signals according to the image sensing signals; and a clock generation circuit, comprising: a first RC circuit, comprising a first capacitor, coupled to a first predetermined voltage level and a second predetermined voltage level; a first switch, coupled to the first RC circuit; a second RC circuit, comprising a second capacitor, coupled to the first switch; a second switch, coupled to the second RC circuit; a comparator, comprising: a first input terminal, coupled to the second RC circuit and the second switch; a second input terminal, configured to receive a reference voltage level; and an output terminal, coupled to a control terminal of the first switch and a control terminal of the second switch; and a logic circuit, coupled to the output terminal of the comparator, configured to generate a clock signal to at least one of the pixel array, the reading circuit and the ADC; wherein the first RC circuit is provided outside an IC; wherein the first switch, the second RC circuit, the second switch, the comparator and the logic circuit are provided inside the IC.