# US 12,224,957 B2 · Communication apparatus and reference signal reception method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,224,957 B2 - Document ID: US12224957B2 - Status: Granted - Kind: B2 - Application number: 18/630,875 - Filed: 2024-04-09 - Published: 2024-08-01 - Granted: 2025-02-11 - Earliest claimed: 2009-01-29 - Assignees: Sun Patent Trust - Applicants: Sun Patent Trust - Inventors: Takashi Iwai; Sadaki Futagi; Tomohumi Takata; Daichi Imamura; Yoshihiko Ogawa - Web page: https://patentgrep.com/patent/US12224957B2 ## CPC - H04L 5/0048: {Allocation of pilot signals, i.e. of signals known to the receiver (allocation of control signalling H04L5/0053; use of control signalling H04L5/0091)} - H04L 25/0226: {sounding signals per se} - H04L 27/2613: {Structure of the reference signals} - H04L 25/022: {of frequency response} - H04L 25/03159: {operating in the frequency domain (H04L25/03165, H04L25/03178 take precedence)} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract Disclosed are a wireless transmitter and a reference signal transmission method that improve channel estimation accuracy. In a terminal, which transmits a reference signal using n (n is a non-negative integer 2 or greater) band blocks (which correspond to clusters here), which are disposed with spaces therebetween in a frequency direction, a reference signal controller switches the reference signal formation method of a reference signal generator between a first formation method and a second formation method based on the number (n) of band blocks. In addition, a threshold value setting unit adjusts a switching threshold value based on the frequency spacing between band blocks. Thus, the reference signal formation method can be selected with good accuracy and, as a result, channel estimation accuracy is further improved. ## Claims ### Claim 1 An integrated circuit to control a process, the process comprising: transmitting, to a terminal, allocation information indicating one or more sets of consecutive frequency resources allocated in each of one or more uplink component carriers, which include a first component carrier and a second component carrier, the first component carrier and the second component carrier having different frequencies, and more than one set of consecutive frequency resources, of said one or more sets of consecutive frequency resources, being spaced apart from each other along a frequency axis; and receiving one uplink reference signal sequence or plural uplink reference signal sequences from the terminal that performs, based on the allocation information, one operation selected from two operations including: a first operation of generating the plural uplink reference signal sequences including a first sequence and a second sequence, mapping the generated first sequence in said one or more sets of consecutive frequency resources allocated in the first component carrier, mapping the generated second sequence in said one or more sets of consecutive frequency resources allocated in the second component carrier, and controlling transmission of the mapped first sequence and the mapped second sequence; and a second operation of generating the one uplink reference signal sequence, mapping the generated one uplink reference signal sequence in said more than one set of consecutive frequency resources allocated in said one uplink component carrier by dividing the generated one uplink reference signal sequence into more subsequences correspondingly to said more than one set of consecutive frequency resources, respectively, and controlling transmission of the mapped one uplink reference signal sequence. ### Claim 2 (depends on 1) The integrated circuit according to claim 1, comprising: circuitry which, in operation, controls the process; at least one input coupled to the circuitry, wherein the at least one input, in operation, inputs data; and at least one output coupled to the circuitry, wherein the at least one output, in operation, outputs data. ### Claim 3 (depends on 1) The integrated circuit according to claim 1, wherein the one uplink reference signal sequence or plural uplink reference signal sequences are cyclic shift sequences. ### Claim 4 (depends on 1) The integrated circuit according to claim 1, wherein when a number of said one or more uplink component carriers is two, a number of the plural uplink reference signal sequences is two. ### Claim 5 (depends on 1) The integrated circuit according to claim 1, wherein a sequence number of the first sequence is different from a sequence number of the second sequence. ### Claim 6 (depends on 1) The integrated circuit according to claim 1, wherein a first length of the first sequence corresponds to a bandwidth of the one or more sets of consecutive frequency resources allocated in the first component carrier, and a second length of the second sequence corresponds to a bandwidth of the one or more sets of consecutive frequency resources allocated in the second component carrier. ### Claim 7 (depends on 1) The integrated circuit according to claim 1, wherein a length of the first sequence mapped in one set of consecutive frequency resources allocated in the first component carrier is different from a length of the second sequence mapped in more sets of consecutive frequency resources allocated in the second component carrier. ### Claim 8 An integrated circuit comprising circuitry, which, in operation: controls transmitting, to a terminal, allocation information indicating one or more sets of consecutive frequency resources allocated in each of one or more uplink component carriers, which include a first component carrier and a second component carrier, the first component carrier and the second component carrier having different frequencies, and more than one set of consecutive frequency resources, of said one or more sets of consecutive frequency resources, being spaced apart from each other along a frequency axis; and controls receiving one uplink reference signal sequence or plural uplink reference signal sequences from the terminal that performs, based on the allocation information, one operation selected from two operations including: a first operation of generating the plural uplink reference signal sequences including a first sequence and a second sequence, mapping the generated first sequence in said one or more sets of consecutive frequency resources allocated in the first component carrier, mapping the generated second sequence in said one or more sets of consecutive frequency resources allocated in the second component carrier, and controlling transmission of the mapped first sequence and the mapped second sequence; and a second operation of generating the one uplink reference signal sequence, mapping the generated one uplink reference signal sequence in said more than one set of consecutive frequency resources allocated in said one uplink component carrier by dividing the generated one uplink reference signal sequence into more subsequences correspondingly to said more than one set of consecutive frequency resources, respectively, and controlling transmission of the mapped one uplink reference signal sequence. ### Claim 9 (depends on 8) The integrated circuit according to claim 8, comprising: at least one input coupled to the circuitry, wherein the at least one input, in operation, inputs data; and at least one output coupled to the circuitry, wherein the at least one output, in operation, outputs data. ### Claim 10 (depends on 8) The integrated circuit according to claim 8, wherein the one uplink reference signal sequence or plural uplink reference signal sequences are cyclic shift sequences. ### Claim 11 (depends on 8) The integrated circuit according to claim 8, wherein when a number of said one or more uplink component carriers is two, a number of the plural uplink reference signal sequences is two. ### Claim 12 (depends on 8) The integrated circuit according to claim 8, wherein a sequence number of the first sequence is different from a sequence number of the second sequence. ### Claim 13 (depends on 8) The integrated circuit according to claim 8, wherein a first length of the first sequence corresponds to a bandwidth of the one or more sets of consecutive frequency resources allocated in the first component carrier, and a second length of the second sequence corresponds to a bandwidth of the one or more sets of consecutive frequency resources allocated in the second component carrier. ### Claim 14 (depends on 8) The integrated circuit according to claim 8, wherein a length of the first sequence mapped in one set of consecutive frequency resources allocated in the first component carrier is different from a length of the second sequence mapped in more sets of consecutive frequency resources allocated in the second component carrier.