# US 12,224,774 B2 · Runtime reconfigurable compression format conversion > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,224,774 B2 - Document ID: US12224774B2 - Status: Granted - Kind: B2 - Application number: 18/096,551 - Filed: 2023-01-12 - Published: 2024-05-16 - Granted: 2025-02-11 - Earliest claimed: 2022-11-16 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jong Hoon Shin; Ardavan Pedram; Joseph Hassoun - Web page: https://patentgrep.com/patent/US12224774B2 ## CPC - H03M 7/3059: {Digital compression and data reduction techniques where the original information is represented by a subset or similar information, e.g. lossy compression} - G06F 8/4432: {Reducing the energy consumption} - G06F 8/4434: {Reducing the memory space required by the program code} - G06N 3/0495: Quantised networks; Sparse networks; Compressed networks - H03M 7/3079: {Context modeling} - H03M 7/6011: {Encoder aspects} - H03M 7/6064: {Selection of Compressor} - H03M 7/6094: {according to reasons other than compression rate or data type} - G06N 3/063: using electronic means - H03M 7/46: Conversion to or from run-length codes, i.e. by representing the number of consecutive digits, or groups of digits, of the same kind by a code word and a digit indicative of that kind - H03M 7/6017: {Methods or arrangements to increase the throughput} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract A runtime data-format optimizer for a processing element includes a sparsity-detector and a compression-converter. The sparsity-detector selects a first compression-conversion format during a runtime of the processing element based on a performance model that is based on a first sparsity pattern of first data stored in a first memory that is exterior to the processing element and a second sparsity pattern of second data that is to be stored in a second memory within the processing element. The second sparsity pattern is based on a runtime configuration of the processing element. The first data is stored in the first memory using a first compression format and the second data is to be stored in the second memory using a second compression format. The compression-conversion circuit converts the first compression format of the first data to be the second compression format of the second data based on the first compression-conversion format. ## Claims ### Claim 1 A data-format optimizer for a processing element, comprising: a sparsity-detection circuit configured to select a first compression-conversion format during a runtime of the processing element based, at least in part, on a first performance model that is based on a first sparsity pattern of first data stored in a first memory that is exterior to the processing element and a second sparsity pattern of second data that is to be stored in a second memory within the processing element, the second sparsity pattern being based on a runtime configuration of the processing element, the first data being stored in the first memory using a first compression format and the second data to be stored in the second memory using a second compression format; and a compression-conversion circuit configured to convert the first compression format of the first data to be the second compression format of the second data based on the first compression-conversion format. ### Claim 2 (depends on 1) The data-format optimizer of claim 1, wherein the first performance model further includes a latency associated with converting the first data to the second data. ### Claim 3 (depends on 2) The data-format optimizer of claim 2, wherein the first performance model further includes an energy consumption associated with converting the first data to the second data. ### Claim 4 (depends on 1) The data-format optimizer of claim 1, wherein the first performance model further includes an energy consumption associated with converting the first data to the second data. ### Claim 5 (depends on 1) The data-format optimizer of claim 1, wherein the sparsity-detection circuit is further configured to select a second compression-conversion format during runtime of the processing element based, at least in part, on a second performance model that is based on a third sparsity pattern of output data stored in a third memory within the processing element; and wherein the compression-conversion circuit configured to convert the output data to a third compression format that is based on the second compression-conversion format for storage in the first memory. ### Claim 6 (depends on 1) The data-format optimizer of claim 1, wherein the sparsity-detection circuit is further configured to generate two or more performance models from which the first performance model is selected. ### Claim 7 (depends on 6) The data-format optimizer of claim 6, wherein the sparsity-detection circuit is configured to sample the first sparsity pattern of first data to generate the two or more performance models. ### Claim 8 (depends on 7) The data-format optimizer of claim 7, wherein the sparsity-detection circuit is configured to generate the two or more performance models further based on sparsity operational modes of the processing element. ### Claim 9 (depends on 1) The data-format optimizer of claim 1, wherein at least one of the first compression format and the second compression format comprises a Run Length Encoding (RLE), a Zero Value Compression (ZVC), a Compressed Sparse Column (CSC) encoding, or a Compressed Sparse Row (CSR) encoding. ### Claim 10 A data-format optimizer for a processing element, comprising: a sparsity-detection circuit configured to generate, during a runtime of the processing element, at least one or more performance models that are based on a first sparsity pattern of first data stored in a first memory and a second sparsity pattern of second data that is to be stored in a second memory, the first memory being exterior to the processing element and the second memory being within the processing element, and to determine a first compression-conversion format based, at least in part, a selection of the one or more performance models; and a compression-conversion circuit configured to apply the first compression-conversion format to the first data to become the second data. ### Claim 11 (depends on 10) The data-format optimizer of claim 10, wherein the sparsity-detection circuit is configured to sample the first sparsity pattern of the first data to generate the one or more performance models. ### Claim 12 (depends on 11) The data-format optimizer of claim 11, wherein the sparsity-detection circuit is configured to generate the one or more performance models further based on sparsity operational modes of the processing element. ### Claim 13 (depends on 10) The data-format optimizer of claim 10, wherein each performance model includes a latency associated with converting the first data to the second data. ### Claim 14 (depends on 13) The data-format optimizer of claim 13, wherein at least one performance model further includes an energy consumption associated with converting the first data to the second data. ### Claim 15 (depends on 10) The data-format optimizer of claim 10, wherein at least one performance model further includes an energy consumption associated with converting the first data to the second data. ### Claim 16 (depends on 10) The data-format optimizer of claim 10, wherein the sparsity-detection circuit is further configured to select a second compression-conversion format during the runtime of the processing element based, at least in part, on a second performance model that is based on a third sparsity pattern of output data stored in a third memory within the processing element; and wherein the compression-conversion circuit configured to convert the output data to a third compression format that is based on the second compression-conversion format for storage in the first memory. ### Claim 17 (depends on 10) The data-format optimizer of claim 10, wherein the first compression format comprises a Run Length Encoding (RLE), a Zero Value Compression (ZVC), a Compressed Sparse Column (CSC) encoding, or a Compressed Sparse Row (CSR) encoding.