# US 12,224,771 B2 · Data reliability for extreme temperature usage conditions in data storage

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- Number: US 12,224,771 B2
- Document ID: US12224771B2
- Status: Granted
- Kind: B2
- Application number: 18/513,278
- Filed: 2023-11-17
- Published: 2024-03-14
- Granted: 2025-02-11
- Earliest claimed: 2020-07-23
- Assignees: Lodestar Licensing Group LLC
- Applicants: Lodestar Licensing Group LLC
- Inventors: Poorna Kale; Christopher Joseph Bueb
- Web page: https://patentgrep.com/patent/US12224771B2

## CPC

- H03M 13/2906: {using block codes (H03M13/2957 takes precedence)}
- H03M 13/356: {Unequal error protection [UEP]}
- G06F 11/1012: {using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence)}
- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- H03M 13/29: combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M 13/353: {Adaptation to the channel}
- G06N 3/02: Neural networks
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- H03M 13/1102: {Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes}
- H03M 13/1515: {Reed-Solomon codes}
- H03M 13/19: Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
- H03M 13/2957: {Turbo codes and decoding}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

After data to be written to a storage device, such as a solid state drive (SSD), is received from a host system, the received data is encoded using a first error correction code to generate first parity data. A temperature at which memory cells of the storage device will store the received data is determined. In response, a first portion of the received data is identified (e.g., data in memory storage that is error-prone at a predicted higher temperature that has been determined based on output from an artificial neural network using sensor(s) input). The first portion is encoded using a second error correction code to generate second parity data. The second error correction code has a higher error correction capability than the first error correction code. The encoded first portion, the first parity data, and the second parity data are stored in the memory cells.

## Claims

### Claim 1

A device, comprising:
an array of non-volatile memory cells; and
a logic circuit configured to:
determine a condition of storing a set of data in the non-volatile memory cells for retrieval;
select, based on the condition, a level of redundancy configured to protect the set of data via error correction techniques;
generate, based on the level selected for the condition, redundant data; and
store, in the non-volatile memory cells, the set of data and the redundant data.

### Claim 2 (depends on 1)

The device of claim 1, wherein the redundant data includes parity data.

### Claim 3 (depends on 1)

The device of claim 1, wherein the condition includes a temperature.

### Claim 4 (depends on 1)

The device of claim 1, wherein the condition includes a level of processing power to decode using the error correction techniques.

### Claim 5 (depends on 1)

The device of claim 1, wherein the condition includes a condition of power supply.

### Claim 6 (depends on 1)

The device of claim 1, wherein the logic circuit is operable to generate redundant data at a first predetermined level and a second predetermined level higher than the first predetermined level.

### Claim 7 (depends on 6)

The device of claim 6, wherein the logic circuit is operable to generate first parity data from first data to protect the first data at the first predetermined level, and generate the first parity data and second parity data from the first data to protect the first data at the second predetermined level.

### Claim 8 (depends on 1)

The device of claim 1, wherein the condition is determined based on a machine learning model and sensor data.

### Claim 9 (depends on 8)

The device of claim 8, further comprising:
a sensor configured to generate inputs to the machine learning mode to generate a prediction indicative of the condition.

### Claim 10

A method, comprising:
determining, by a computing device, a condition of storing a set of data in an array of non-volatile memory cells of the computing device for retrieval;
selecting, by the computing device based on the condition, a level of redundancy configured to protect the set of data via error correction techniques;
generating, by the computing device based on the level selected for the condition, redundant data; and
storing, in the non-volatile memory cells, the set of data and the redundant data.

### Claim 11 (depends on 10)

The method of claim 10, wherein the redundant data includes parity data.

### Claim 12 (depends on 10)

The method of claim 10, wherein the condition includes a temperature.

### Claim 13 (depends on 10)

The method of claim 10, wherein the condition includes a level of processing power to decode using the error correction techniques.

### Claim 14 (depends on 10)

The method of claim 10, wherein the condition includes a condition of power supply.

### Claim 15 (depends on 10)

The method of claim 10, wherein the computing device is operable to generate redundant data at a first predetermined level and a second predetermined level higher than the first predetermined level.

### Claim 16 (depends on 15)

The method of claim 15, wherein generation of redundant data at the first predetermined level includes generating first parity data from first data to protect the first data at the first predetermined level, and generation of redundant data at the second predetermined level includes generating the first parity data and second parity data from the first data to protect the first data at the second predetermined level.

### Claim 17 (depends on 10)

The method of claim 10, wherein the condition is determined based on a machine learning model and sensor data.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
generating, by a sensor configured in the computing device, inputs to the machine learning mode to generate a prediction indicative of the condition.

### Claim 19

A non-transitory computer storage medium storing instructions which when executed by a computing device, cause the computing device to perform a method, comprising:
determining, by the computing device, a condition of storing a set of data in an array of non-volatile memory cells of the computing device for retrieval;
selecting, by the computing device based on the condition, a level of redundancy configured to protect the set of data via error correction techniques;
generating, by the computing device based on the level selected for the condition, redundant data; and
storing, in the non-volatile memory cells, the set of data and the redundant data.

### Claim 20 (depends on 19)

The non-transitory computer storage medium of claim 19, wherein the generating of the redundant data at a first predetermined level includes generating first parity data from first data to protect the first data at the first predetermined level; and
wherein the generating of the redundant data at a second predetermined level includes generating the first parity data and second parity data from the first data to protect the first data at the second predetermined level.
