# US 12,224,767 B2 · Signal processing apparatus for use in optical communication > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,224,767 B2 - Document ID: US12224767B2 - Status: Granted - Kind: B2 - Application number: 18/167,380 - Filed: 2023-02-10 - Published: 2023-06-15 - Granted: 2025-02-11 - Earliest claimed: 2020-08-13 - Assignees: Huawei Technologies Co., Ltd. - Applicants: Huawei Technologies Co., Ltd. - Inventors: Artem Vitalyevich Cherenkov; Man Zhao; Mikhail Alexandrovich Linnik; Yijie Wang - Web page: https://patentgrep.com/patent/US12224767B2 ## CPC - H03M 1/662: {Multiplexed conversion systems} - H03M 1/0624: {by synchronisation} - H03M 1/0854: {of quantisation noise} - H03M 1/1028: {at two points of the transfer characteristic, i.e. by adjusting two reference values, e.g. offset and gain error (gain setting for range control H03M1/18)} - H03M 1/1033: {over the full range of the converter, e.g. for correcting differential non-linearity} - H03M 1/181: {in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A signal processing apparatus includes a plurality of time-interleaving digital-to-analog converters each configured to sample a digital input signal at a preset sub-DAC sample frequency, and to generate an analog sub-DAC output signal. The signal processing apparatus includes analog multiplexer that samples the plurality of sub-DAC output signals at a preset multiplexer clock frequency and generates a multiplexer output signal. The signal processing apparatus further includes a local ADC that receives the multiplexer output signal and generate a digital feedback signal. The signal processing apparatus further includes a digital compensation engine that receives the digital feedback signal from the local ADC and determine one or more distortion compensation parameters. The signal processing apparatus further includes a digital pre-processing stage that receives the one or more distortion compensation parameters from the digital compensation engine and performs distortion compensation pre-processing on the digital input signal. ## Claims ### Claim 1 A signal processing apparatus, comprising: a plurality of time-interleaving digital-to-analog converters (sub-DACs), each configured to sample a digital input signal at a preset sub-DAC sample frequency, and to generate an analog sub-DAC output signal; an analog multiplexer configured to sample the plurality of sub-DAC output signals at a preset multiplexer clock frequency, and to generate a multiplexer output signal; a local analog-to-digital converter (ADC), configured to receive the multiplexer output signal and generate a digital feedback signal; a digital compensation engine configured to receive the digital feedback signal from the local ADC and determine one or more distortion compensation parameters based on a comparison of the digital feedback signal with the digital input signal; and a digital pre-processing stage configured to receive the one or more distortion compensation parameters from the digital compensation engine and perform distortion compensation pre-processing on the digital input signal. ### Claim 2 (depends on 1) The signal processing apparatus of claim 1, wherein the digital pre-processing stage is configured to perform the distortion compensation pre-processing online. ### Claim 3 (depends on 1) The signal processing apparatus of claim 1, wherein the distortion compensation parameters include one or more sub-DAC sample frequency parameters. ### Claim 4 (depends on 3) The signal processing apparatus of claim 3, further comprising a sub-DAC time-delay controller, configured to receive the one or more sub-DAC sample frequency parameters, and to adjust a respective time-delay for each sub-DAC. ### Claim 5 (depends on 1) The signal processing apparatus of claim 1, wherein the distortion compensation parameters include one or more sub-DAC non-linearity parameters, and the digital compensation engine is configured to determine the sub-DAC non-linearity parameters based on parameters of a memory-less spline digital pre-distorter model. ### Claim 6 (depends on 4) The signal processing apparatus of claim 4, wherein the distortion compensation parameters include one or more sub-DAC gain parameters. ### Claim 7 (depends on 6) The signal processing apparatus of claim 6, wherein the distortion compensation parameters include one or more sub-DAC voltage offset parameters. ### Claim 8 (depends on 7) The signal processing apparatus of claim 7, further comprising: a single tone generator configured to output a single frequency sample tone to the digital pre-processing stage; and a power detector configured to receive the multiplexer output signal and generate a power feedback signal; wherein the digital compensation engine is configured to receive the power feedback signal from the power detector and determine one or more of the sub-DAC voltage offset parameters based on a comparison of the power feedback signal with the single frequency sample tone. ### Claim 9 (depends on 8) The signal processing apparatus of claim 8, wherein the single tone generator is configured to output the single frequency sample tone while the digital input signal is not input to the digital pre-processing stage. ### Claim 10 (depends on 9) The signal processing apparatus of claim 9, further comprising a sub-DAC voltage controller, configured to receive the one or more sub-DAC gain parameters and/or sub-DAC voltage offset parameters, and to adjust a respective gain and/or voltage offset for each sub-DAC. ### Claim 11 (depends on 1) The signal processing apparatus of claim 1, wherein the local ADC is configured to sample the multiplexer output signal at a preset sampling frequency which is substantially smaller than the multiplexer clock frequency. ### Claim 12 (depends on 1) The signal processing apparatus of claim 1, further comprising: a pseudorandom noise generator configured to generate noise in an out-of-band region of the digital input signal.