# US 12,224,765 B1 · SAR ADC capable of full-scale voltage auto-tuning and method for the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,224,765 B1 - Document ID: US12224765B1 - Status: Granted - Kind: B1 - Application number: 18/194,172 - Filed: 2023-03-31 - Granted: 2025-02-11 - Earliest claimed: 2023-03-31 - Assignees: Pixart Imaging Incorporation - Applicants: PixArt Imaging Incorporation - Inventors: Boon-Eu Seow; Kei-Tee Tiew - Web page: https://patentgrep.com/patent/US12224765B1 ## CPC - H03M 1/18: Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging - H03M 1/1061: {using digitally programmable trimming circuits} - H03M 1/38: sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) - H03M 1/466: {using switched capacitors} - H03M 1/468: {in which the input S/H circuit is merged with the feedback DAC array} - H03M 1/804: {with charge redistribution} - H03M 1/00: Analogue/digital conversion; Digital/analogue conversion (conversion of analogue values to or from differential modulation H03M3/00) - H03M 1/12: Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) - H03M 1/124: {Sampling or signal conditioning arrangements specially adapted for A/D converters} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract An SAR ADC includes: at least one sub-ADC, configured to convert a corresponding input signal to a corresponding SAR code; and a tuning control unit, configured to adjust a full-scale voltage (VFS) of each of the sub-ADC to a corresponding predetermined target level in a VFS tuning mode. The tuning control unit generates a tuning code to control an adjusting capacitor array coupled to the sub-ADC for tuning the VFS. The tuning control unit controls the sub-ADC to convert plural reference voltages in the VFS tuning mode and extrapolating the conversion result to determine a corresponding calibrating VFS. The tuning control unit determines whether the calibrating VFS meeting the target VFS and loops the adjusting process in a linear search method or in a SAR method. ## Claims ### Claim 1 A successive approximation register analog-to-digital converter (SAR ADC), comprising: at least one sub-ADC, wherein each of the at least one sub-ADC is configured to convert a corresponding input signal to a corresponding SAR code; and a tuning control unit, configured to adjust a full-scale voltage of each of the sub-ADC to a corresponding predetermined target level in a VFS tuning mode; wherein each of the at least one sub-ADC includes: a sample-and-hold circuit, configured to operably generate a sample-and-hold signal by sample-and-holding the input signal; a capacitive digital-to-analog converter (CDAC), configured to operably generate a DAC output signal according to the SAR code; a comparator, configured to operably compare the sample-and-hold signal and the DAC output signal to generate a comparison signal; a SAR logic circuit, configured to operably generate the SAR code according to the comparison signal using a binary successive approximation register conversion method; and an adjusting capacitor array, coupled to an output terminal of the CDAC and configured to operably adjust an equivalent capacitance on the output terminal of the CDAC; wherein in the VFS tuning mode, the tuning control unit is configured to operably generate a capacitor tuning code to adjust the equivalent capacitance on the output terminal of the CDAC, so as to adjust a full-scale voltage of each of the at least one sub-ADC to the predetermined target level according to the following steps: S100: setting the capacitor tuning code to an initial code; S201: adjusting the input signal to plural reference voltages; S202: controlling the sub-ADC to convert the plural reference voltages to corresponding plural digital reference codes; S203: extrapolating plural pairs of the plural reference voltages versus the plural digital reference codes to obtain a calibrating full-scale voltage corresponding to the capacitor tuning code; S300: determining whether a difference between the calibrating full-scale voltage and the predetermined full-scale voltage level is meeting a target, wherein if the difference is meeting the target, entering a step S800, else entering a step S400; S400: updating the capacitor tuning code according to the difference and return to the step S201; and S800: memorizing the capacitor tuning code for the sub-ADC to operate with the full-scale voltage having the predetermined target level in a normal operation mode. ### Claim 2 (depends on 1) The SAR ADC of claim 1, wherein the step of updating the capacitor tuning code is achieved by a linear search method or by a binary successive approximation method. ### Claim 3 (depends on 1) The SAR ADC of claim 1, wherein a count of the plural reference voltages is equal to or higher than 3. ### Claim 4 (depends on 1) The SAR ADC of claim 1, wherein the step S203 further includes: extrapolating the plural pairs of the plural reference voltages versus the plural digital reference codes to obtain an offset of the SAR DAC corresponding to the capacitor tuning code; wherein the calibrating full-scale voltage is obtained by extrapolation after compensating the offset. ### Claim 5 (depends on 1) The SAR ADC of claim 1, wherein the adjusting capacitor array includes binary-weighted capacitors which are controlled by the capacitor tuning code. ### Claim 6 (depends on 1) The SAR ADC of claim 1, wherein the calibrating full-scale voltage decreases in response to the increasing of the equivalent capacitance on the output terminal of the CDAC. ### Claim 7 (depends on 1) The SAR ADC of claim 1, wherein the plural reference voltages are arranged in an arithmetic series. ### Claim 8 (depends on 7) The SAR ADC of claim 7, wherein one of the plural reference voltages is 0V. ### Claim 9 (depends on 1) The SAR ADC of claim 1, wherein all the plural reference voltages are smaller than the predetermined full-scale voltage level. ### Claim 10 (depends on 1) The SAR ADC of claim 1, wherein each of the sub-ADC is configured to operate in a monotonic switching method or in a switch-back switching method. ### Claim 11 A method for automatically tuning a full-scale voltage of a successive approximation register analog-to-digital converter (SAR ADC), wherein the SAR ADC includes a sample-and-hold circuit for generating a sample-and-hold signal by sample-and-holding the input signal; a capacitive digital-to-analog converter (CDAC) for generating a DAC output signal according to the SAR code; a comparator for comparing the sample-and-hold signal and the DAC output signal to generate a comparison signal; and a SAR logic circuit for generating the SAR code according to the comparison signal using a binary successive approximation register conversion method; the method comprising: providing a VFS adjusting means which is controlled by a tuning code for adjusting the full-scale voltage of the SAR ADC; and generating the tuning code to control the VFS adjusting means, so as to tune the full-scale voltage of the SAR ADC to a predetermined target level in a VFS tuning mode according to the following steps: S100: setting the tuning code to an initial code; S201: adjusting the input signal to plural reference voltages; S202: controlling the sub-ADC to convert the plural reference voltages to plural digital reference codes; S203: extrapolating plural pairs of the plural reference voltages versus the plural digital reference codes to obtain a calibrating full-scale voltage corresponding to the tuning code; S300: determining whether a difference between the calibrating full-scale voltage and the predetermined full-scale voltage level is meeting a target, wherein if the difference is meeting the target, entering a step S800, else entering a step S400; S400: updating the tuning code according to the difference and return to the step S201; and S800: memorizing the tuning code for the sub-ADC to operate with the full-scale voltage having the predetermined target level in a normal operation mode. ### Claim 12 (depends on 11) The method of claim 11, wherein the step of updating the tuning code is achieved by a linear search method or by a binary successive approximation method. ### Claim 13 (depends on 11) The method of claim 11, wherein a count of the plural reference voltages is equal to or higher than 3. ### Claim 14 (depends on 11) The method of claim 11, wherein the step S203 further includes: extrapolating the plural pairs of the plural reference voltages versus the plural digital reference codes to obtain an offset of the SAR DAC corresponding to the tuning code; wherein the calibrating full-scale voltage is obtained by extrapolation after compensating the offset. ### Claim 15 (depends on 11) The method of claim 11, wherein the VFS adjusting means includes binary-weighted capacitors which are controlled by the tuning code. ### Claim 16 (depends on 15) The method of claim 15, wherein the calibrating full-scale voltage decreases in response to the increasing of the equivalent capacitance on the output terminal of the CDAC. ### Claim 17 (depends on 11) The method of claim 11, wherein the plural reference voltages are arranged in an arithmetic series. ### Claim 18 (depends on 17) The method of claim 17, wherein one of the plural reference voltages is 0V. ### Claim 19 (depends on 11) The method of claim 11, wherein all the plural reference voltages are smaller than the predetermined full-scale voltage level. ### Claim 20 (depends on 11) The method of claim 11, wherein SAR ADC is configured to operably operate in a monotonic switching method or in a switch-back switching method.