# US 12,224,756 B2 · Clock and data recovery circuit using neural network circuit to obtain frequency difference information

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- Number: US 12,224,756 B2
- Document ID: US12224756B2
- Status: Granted
- Kind: B2
- Application number: 18/103,472
- Filed: 2023-01-30
- Published: 2024-01-04
- Granted: 2025-02-11
- Earliest claimed: 2022-07-04
- Assignees: Mediatek Inc.
- Applicants: Mediatek Inc.
- Inventors: Chien-Kai Kao; Shih-Che Hung; Tse-Hsien Yeh
- Web page: https://patentgrep.com/patent/US12224756B2

## CPC

- H03L 7/0807: {concerning mainly a recovery circuit for the reference signal}
- G06N 3/063: using electronic means
- H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS

## Abstract

The present invention includes a CDR circuit including a phase detector, a neural network circuit, a controller and a clock signal generator is disclosed. The phase detector is configured to use a clock signal to sample an input signal to generate a plurality of phase detection results. The neural network circuit is coupled to the phase detector, and is configured to receive the plurality of phase detection results to determine information of a frequency difference between the clock signal and the input signal. The controller is configured to generate a control signal according to the information of the frequency difference between the clock signal and the input signal. The clock signal generator is configured to use the control signal to adjust a phase or frequency of the clock signal outputted to the phase detector.

## Claims

### Claim 1

A clock and data recovery (CDR) circuit, comprising:
a phase detector, configured to use a clock signal to sample an input signal to generate a plurality of phase detection results;
a neural network circuit, coupled to the phase detector, configured to receive the plurality of phase detection results to determine information of a frequency difference between the clock signal and the input signal;
a controller, configured to generate a control signal according to the information of the frequency difference between the clock signal and the input signal; and
a clock signal generator, configured to use the control signal to adjust a phase or frequency of the clock signal outputted to the phase detector.

### Claim 2 (depends on 1)

The CDR circuit of claim 1, wherein before the neural network circuit generates the information of the frequency difference between the clock signal and the input signal, the controller does not generate the control signal to control the clock signal generator to adjust the phase of the clock signal; and after the neural network circuit generates the information of the frequency difference between the clock signal and the input signal, the controller starts to generate the control signal to control the clock signal generator to adjust the phase or frequency of the clock signal.

### Claim 3 (depends on 2)

The CDR circuit of claim 2, wherein after the neural network circuit generates the information of the frequency difference between the clock signal and the input signal, the neural network circuit enters a sleep mode.

### Claim 4 (depends on 1)

The CDR circuit of claim 1, wherein the neural network circuit groups the plurality of phase detection results to obtain a plurality of nodes, and performs an autocorrelation operation on at least part of the plurality of nodes to determine two nodes that are orthogonal, and determines the information of the frequency difference between the clock signal and the input signal according to the two nodes.

### Claim 5 (depends on 1)

The CDR circuit of claim 1, further comprising:
a pattern filter, configured to filter the plurality of phase detection results to generate a plurality of filtered phase detection results;
wherein the neural network circuit receives the plurality of filtered phase detection results to determine the information of the frequency difference between the clock signal and the input signal.

### Claim 6 (depends on 1)

The CDR circuit of claim 1, further comprising:
a demultiplexer, configured to convert the plurality of phase detection results into parallel data;
wherein the neural network circuit receives the parallel data to determine the information of the frequency difference between the clock signal and the input signal.

### Claim 7 (depends on 6)

The CDR circuit of claim 6, further comprising
a pattern filter, configured to filter the parallel data to generate a plurality of filtered phase detection results;
wherein the neural network circuit receives the plurality of filtered phase detection results to determine the information of the frequency difference between the clock signal and the input signal.

### Claim 8

A signal processing method of a clock and data recovery (CDR) circuit, comprising:
using a clock signal to sample an input signal to generate a plurality of phase detection results;
using a neural network circuit to receive the plurality of phase detection results to determine information of a frequency difference between the clock signal and the input signal;
generating a control signal according to the information of the frequency difference between the clock signal and the input signal; and
using the control signal to adjust a phase or frequency of the clock signal.

### Claim 9 (depends on 8)

The signal processing method of claim 8, further comprising:
before the neural network circuit generates the information of the frequency difference between the clock signal and the input signal, not generating the control signal to adjust the phase or frequency of the clock signal; and
after the neural network circuit generates the information of the frequency difference between the clock signal and the input signal, starting to generate the control signal to adjust the phase or frequency of the clock signal.

### Claim 10 (depends on 9)

The signal processing method of claim 9, further comprising:
after the neural network circuit generates the information of the frequency difference between the clock signal and the input signal, controlling the neural network circuit to enter a sleep mode.

### Claim 11 (depends on 8)

The signal processing method of claim 8, wherein the step of using the neural network circuit to receive the plurality of phase detection results to determine information of the frequency difference between the clock signal and the input signal comprises:
grouping the plurality of phase detection results to obtain a plurality of nodes;
performing an autocorrelation operation on at least part of the plurality of nodes to determine two nodes that are orthogonal; and
determining the information of the frequency difference between the clock signal and the input signal according to the two nodes.

### Claim 12 (depends on 8)

The signal processing method of claim 8, further comprising:
filtering the plurality of phase detection results to generate a plurality of filtered phase detection results;
wherein the step of using the neural network circuit to receive the plurality of phase detection results to determine the information of the frequency difference between the clock signal and the input signal comprises:
using the neural network circuit to receive the plurality of filtered phase detection results to determine the information of the frequency difference between the clock signal and the input signal.

### Claim 13 (depends on 8)

The signal processing method of claim 8, further comprising:
converting the plurality of phase detection results into parallel data;
wherein the step of using the neural network circuit to receive the plurality of phase detection results to determine the information of the frequency difference between the clock signal and the input signal comprises:
using the neural network circuit to receive the parallel data to determine the information of the frequency difference between the clock signal and the input signal.

### Claim 14 (depends on 13)

The signal processing method of claim 13, further comprising
filtering the parallel data to generate a plurality of filtered phase detection results;
wherein the step of using the neural network circuit to receive the plurality of phase detection results to determine the information of the frequency difference between the clock signal and the input signal comprises:
using the neural network circuit to receive the plurality of filtered phase detection results to determine the information of the frequency difference between the clock signal and the input signal.