# US 12,224,755 B2 · Method of and apparatus for controlling clock signal > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,224,755 B2 - Document ID: US12224755B2 - Status: Granted - Kind: B2 - Application number: 18/489,692 - Filed: 2023-10-18 - Published: 2024-02-08 - Granted: 2025-02-11 - Earliest claimed: 2021-06-21 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.; Tsmc Nanjing Company, Limited - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.; Tsmc Nanjing Company, Limited - Inventors: Huaixin Xian; Liu Han; Jing Ding; Qingchao Meng - Web page: https://patentgrep.com/patent/US12224755B2 ## CPC - H03K 5/135: by the use of time reference signals, e.g. clock signals - G06F 1/04: Generating or distributing clock signals or signals derived directly therefrom - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - H03K 3/037: Bistable circuits - G06F 1/3237: by disabling clock generation or distribution - G06F 2117/04: Clock gating - G06F 2119/12: Timing analysis or timing optimisation - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An integrated circuit includes a clocking transistor, a first enabling transistor, a second enabling transistor, a branch-one transistor, and a branch-two transistor. The first enabling transistor is coupled between the clocking transistor and a first node. The second enabling transistor is coupled between the clocking transistor and a second node. The branch-one transistor is coupled between a first power supply and the first node. The gate terminal of the branch-one transistor is connected to the second node. The branch-two transistor is coupled between the first power supply and the second node. The gate terminal of the branch-two transistor is connected to the first node. Each of the clocking transistor, the first enabling transistor, and the second enabling transistor is a first-type transistor of a reduced threshold. Each of the branch-one transistor and the branch-two transistor is a second-type transistor of a default threshold. ## Claims ### Claim 1 An integrated circuit comprising: a clocking transistor having a gate terminal configured to receive a first clock signal; a first enabling transistor having a semiconductor channel electrically connected between a drain terminal of the clocking transistor and a first node, wherein the first enabling transistor has a gate terminal configured to receive a first enabling signal; a second enabling transistor having a semiconductor channel electrically connected between a drain terminal of the clocking transistor and a second node, wherein the second enabling transistor has a gate terminal configured to receive a second enabling signal which is a logic inverse of the first enabling signal; a branch-one transistor having a semiconductor channel electrically connected between a first power supply and the first node and having a gate terminal electrically connected to the second node, wherein a source terminal of the branch-one transistor is configured to be maintained at a constant supply voltage on the first power supply, wherein the clocking transistor has a source terminal electrically connected to a second power supply; a branch-two transistor having a semiconductor channel electrically connected between the first power supply and the second node and having a gate terminal electrically connected to the first node, wherein a source terminal of the branch-two transistor is configured to be maintained at the constant supply voltage on the first power supply; a clock gating circuit having an output terminal configured to generate a gated clock signal and having a first input terminal configured to receive a latch output signal which is latched to a logic level of either a first node signal at the first node or a second node signal at the second node; and wherein each of the clocking transistor, the first enabling transistor, and the second enabling transistor is a first-type transistor of a reduced threshold, and wherein each of the branch-one transistor and the branch-two transistor is a second-type transistor of a default threshold. ### Claim 2 (depends on 1) The integrated circuit of claim 1, further comprising: a synchronous logic circuit having a clock input configured to receive the gated clock signal generated from a second clock signal by gating the second clock signal with the latch output signal. ### Claim 3 (depends on 1) The integrated circuit of claim 1, wherein the clock gating circuit has a second input terminal configured to receive a second clock signal, and wherein the second clock signal either has a same waveform as the first clock signal or has a logic inverse waveform as the first clock signal. ### Claim 4 (depends on 1) The integrated circuit of claim 1, further comprising: a coupling circuit configured to generate the latch output signal from at least one of a first node signal at the first node or a second node signal at the second node. ### Claim 5 (depends on 1) The integrated circuit of claim 1, further comprising: a first coupling transistor having a gate terminal electrically connected to the second node and having a drain terminal electrically connected to the first node; and a second coupling transistor having a gate terminal electrically connected to the first node and having a drain terminal electrically connected to the second node. ### Claim 6 (depends on 5) The integrated circuit of claim 5, wherein each of the first coupling transistor and the second coupling transistor has a source terminal configured to have a constant voltage. ### Claim 7 (depends on 5) The integrated circuit of claim 5, further comprising: a third coupling transistor having a source terminal electrically connected to the second power supply and having a gate terminal configured to receive a second clock signal, wherein the second clock signal is a logical inverse of the first clock signal; and wherein each of the first coupling transistor and the second coupling transistor has a source terminal electrically connected to a drain terminal of the third coupling transistor. ### Claim 8 (depends on 1) The integrated circuit of claim 1, wherein each of the clocking transistor, the first enabling transistor, and the second enabling transistor is a first-type transistor, wherein each of the branch-one transistor and the branch-two transistor is a second-type transistor, and wherein each first-type transistor is an NMOS transistor and each second-type transistor is a PMOS transistor. ### Claim 9 (depends on 1) The integrated circuit of claim 1, wherein each of the clocking transistor, the first enabling transistor, and the second enabling transistor is a first-type transistor, wherein each of the branch-one transistor and the branch-two transistor is a second-type transistor, and wherein each first-type transistor is an PMOS transistor and each second-type transistor is a NMOS transistor. ### Claim 10 An integrated circuit comprising: a first enabling transistor having a semiconductor channel connected to a first node and having a gate terminal configured to receive a first enabling signal; a second enabling transistor having a semiconductor channel connected to a second node and having a gate terminal configured to receive a second enabling signal which is a logical inverse of the first enabling signal; a plurality of branch-one transistors having semiconductor channels electrically connected in series between a first power supply and the first node, wherein each branch-one transistor has a gate terminal electrically connected to the second node, and wherein one of the branch-one transistors has a source terminal that is configured to be maintained at a constant supply voltage on the first power supply; and a plurality of branch-two transistors having semiconductor channels electrically connected in series between the first power supply and the second node, wherein each branch-two transistor has a gate terminal electrically connected to the first node, and wherein one of the branch-two transistors has a source terminal that is configured to be maintained at the constant supply voltage on the first power supply; and a clocking transistor having a semiconductor channel electrically connected to both a source terminal of the first enabling transistor and a source terminal of the second enabling transistor. ### Claim 11 (depends on 10) The integrated circuit of claim 10, further comprising: a coupling circuit configured to receive at least one of a first node signal from the first node or a second node signal from the second node and further configured to generate a latch output signal which is latched to a logic level of either the first node signal or the second node signal. ### Claim 12 (depends on 11) The integrated circuit of claim 11, further comprising: a synchronous logic circuit having a clock input configured to receive a gated clock signal generated from a second clock signal by gating the second clock signal with the latch output signal. ### Claim 13 (depends on 10) The integrated circuit of claim 10, wherein each of the first enabling transistor, and the second enabling transistor is a first-type transistor, wherein each of the branch-one transistors and the branch-two transistors is a second-type transistor. ### Claim 14 An integrated circuit comprising: a clocking transistor having a gate terminal configured to receive a first clock signal; a first enabling transistor having a semiconductor channel electrically connected between a drain terminal of the clocking transistor and a first node, wherein the first enabling transistor has a gate terminal configured to receive a first enabling signal; a second enabling transistor having a semiconductor channel electrically connected between a drain terminal of the clocking transistor and a second node, wherein the second enabling transistor has a gate terminal configured to receive a second enabling signal which is a logic inverse of the first enabling signal; a branch-one transistor having a semiconductor channel electrically connected between a first power supply and the first node and having a gate terminal electrically connected to the second node, wherein a source terminal of the branch-one transistor is configured to be maintained at a constant supply voltage on the first power supply, wherein the clocking transistor has a source terminal electrically connected to a second power supply; a branch-two transistor having a semiconductor channel electrically connected between the first power supply and the second node and having a gate terminal electrically connected to the first node, wherein a source terminal of the branch-two transistor is configured to be maintained at the constant supply voltage on the first power supply; a clock gating circuit having an output terminal configured to generate a gated clock signal and having a first input terminal configured to receive a latch output signal which is latched to a logic level of either a first node signal at the first node or a second node signal at the second node; and wherein each of the clocking transistor, the first enabling transistor, and the second enabling transistor is a first-type transistor having an enhanced driving strength, the enhanced driving strength being larger than a default driving strength of another first-type transistor. ### Claim 15 (depends on 14) The integrated circuit of claim 14, further comprising: a synchronous logic circuit having a clock input configured to receive the gated clock signal generated from a second clock signal by gating the second clock signal with the latch output signal. ### Claim 16 (depends on 14) The integrated circuit of claim 14, wherein the clock gating circuit has a second input terminal configured to receive a second clock signal, and wherein the second clock signal either has a same waveform as the first clock signal or has a logic inverse waveform as the first clock signal. ### Claim 17 (depends on 14) The integrated circuit of claim 14, further comprising: a coupling circuit configured to generate the latch output signal. ### Claim 18 (depends on 14) The integrated circuit of claim 14, further comprising: a first coupling transistor having a gate terminal electrically connected to the second node and having a drain terminal electrically connected to the first node; and a second coupling transistor having a gate terminal electrically connected to the first node and having a drain terminal electrically connected to the second node. ### Claim 19 (depends on 18) The integrated circuit of claim 18, wherein each of the first coupling transistor and the second coupling transistor has a source terminal configured to have a constant voltage. ### Claim 20 (depends on 18) The integrated circuit of claim 18, further comprising: a third coupling transistor having a source terminal electrically connected to the second power supply and having a gate terminal configured to receive a second clock signal, wherein the second clock signal is a logical inverse of the first clock signal; and wherein each of the first coupling transistor and the second coupling transistor has a source terminal electrically connected to a drain terminal of the third coupling transistor.