# US 12,224,753 B2 · Manufacturing method of an input circuit of a flip-flop

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- Number: US 12,224,753 B2
- Document ID: US12224753B2
- Status: Granted
- Kind: B2
- Application number: 18/365,199
- Filed: 2023-08-03
- Published: 2023-12-21
- Granted: 2025-02-11
- Earliest claimed: 2020-04-01
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Jin-Wei Xu; Hui-Zhong Zhuang; Chih-Liang Chen
- Web page: https://patentgrep.com/patent/US12224753B2

## CPC

- H03K 3/356017: {using additional transistors in the input circuit (H03K3/356104, H03K3/3562 take precedence)}
- H03K 3/356113: {using additional transistors in the input circuit}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 89/10: Integrated device layouts
- H10W 20/43: Layouts of interconnections
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A manufacturing method of an input circuit of a flip-flop including: depositing a first gate strip, a second gate strip, a third gate strip, and a fourth gate strip, wherein a distance between the first and second gate strips, a distance between the second and third gate strips, and a distance between the third and fourth gate strips equal; executing a cut-off operation upon the first gate strip to generate a first first gate strip and a second first gate strip; executing a cut-off operation upon the third gate strip to generate a first third gate strip and a second third gate strip; and directing a first signal to the first first gate strip and the second third gate strip, and a second signal to the second first gate strip and the first third gate strip.

## Claims

### Claim 1

A manufacturing method of an input circuit of a flip-flop, comprising:
depositing a first gate strip, a second gate strip, a third gate strip, and a fourth gate strip;
executing a cut-off operation upon the first gate strip to generate a first first gate strip and a second first gate strip, wherein the first first gate strip is a gate terminal of a first PMOS, and the second first gate strip is a gate terminal of a first NMOS;
executing a cut-off operation upon the third gate strip to generate a first third gate strip and a second third gate strip, wherein the first third gate strip is a gate terminal of a second PMOS and the second third gate strip is a gate terminal of a second NMOS; and
directing a first signal to the first first gate strip and the second third gate strip, and a second signal to the second first gate strip and the first third gate strip;
forming a first conductive strip connected between the first first gate strip and the second third gate; and
forming a second conductive strip connected between the second first gate strip and the first third gate.

### Claim 2 (depends on 1)

The manufacturing method of claim 1, further comprising:
directing a first voltage to a source terminal of the first PMOS; and
directing a second voltage to a source terminal of the first NMOS.

### Claim 3 (depends on 1)

The manufacturing method of claim 1, further comprising:
directing a first voltage to a source terminal of the second PMOS; and
directing a second voltage to a source terminal of the second NMOS.

### Claim 4 (depends on 1)

The manufacturing method of claim 1, wherein the second gate strip is configured to be a co-gate terminal of a third PMOS and a third NMOS, and the third gate strip is configured to be a co-gate terminal of a fourth PMOS and a fourth NMOS, and the manufacturing method further comprises:
forming a conductive line between a source terminal of the first PMOS and a source terminal of the fourth PMOS; and
forming another conductive line between a source terminal of the first NMOS and a source terminal of the fourth NMOS.

### Claim 5

A manufacturing method of an input circuit of a flip-flop, comprising:
forming a first gate strip configured to be a co-gate terminal of a first PMOS and a first NMOS;
forming a second gate strip configured to be a co-gate terminal of a second PMOS and a second NMOS, wherein the first PMOS and the second PMOS share a doping region, and the first NMOs and the second NMOS share a doping region; and
forming a third gate strip configured to be a co-gate terminal of a third PMOS and a third NMOS, wherein the second PMOS and the third PMOS share a doping region, and the second NMOS and the third NMOS share a doping region.

### Claim 6 (depends on 5)

The manufacturing method of claim 5, further comprising:
forming a fourth gate strip, wherein the fourth gate strip is configured to be a gate terminal of a fourth PMOS, and the first PMOS and the fourth PMOS share a doping region; and
forming a fifth gate strip, wherein the fifth gate strip is configured to be a gate terminal of a fourth NMOS, and the third NMOS and the fourth NMOS share a doping region.

### Claim 7 (depends on 6)

The manufacturing method of claim 6, wherein a source terminal of the third PMOS and a source terminal of the fourth PMOS are directed to a first voltage source.

### Claim 8 (depends on 7)

The manufacturing method of claim 7, wherein a source terminal of the first NMOS and a source terminal of the fourth NMOS are directed to a second voltage source.

### Claim 9 (depends on 7)

The manufacturing method of claim 7, wherein the doping region shared by the second NMOS and the third NMOS is directed to a second voltage source.

### Claim 10 (depends on 6)

The manufacturing method of claim 6, wherein doping region shared by the first PMOS and the second PMOS is directed to a first voltage source.

### Claim 11 (depends on 10)

The manufacturing method of claim 10, wherein a source terminal of the first NMOS and a source terminal of the fourth NMOS are directed to a second voltage source.

### Claim 12 (depends on 10)

The manufacturing method of claim 10, wherein the doping region shared by the second NMOS and the third NMOS is directed to a second voltage source.

### Claim 13 (depends on 5)

The manufacturing method of claim 5, further comprising:
forming a fourth gate strip, wherein the fourth gate strip is configured to be a co-gate terminal of a fourth PMOS and a fourth NMOS, the first PMOS and the fourth PMOS share a doping region, and the first NMOS and the fourth NMOS share a doping region.

### Claim 14 (depends on 13)

The manufacturing method of claim 13, wherein a source terminal of the third PMOS and a source terminal of the fourth PMOS are directed to a first voltage source, and the doping region shared by the first NMOS and the fourth NMOS is directed to a second voltage source.

### Claim 15 (depends on 14)

The manufacturing method of claim 14, wherein a drain terminal of the third NMOS is connected to a drain terminal of the fourth NMOS.

### Claim 16

A manufacturing method of an input circuit of a flip flop, comprising:
forming a first first gate strip, wherein the first first gate strip is configured to be a gate terminal of a first PMOS;
forming a second first gate strip, wherein the second first gate strip is configured to be a gate terminal of a first NMOS;
forming a second gate strip, wherein the second gate strip is configured to be a co-gate terminal of a second PMOS and a second NMOS, the first PMOS and the second PMOS share a doping region, and the first NMOS and the second NMOS share a doping region;
forming a first third gate strip, wherein the first third gate strip is configured to be a gate terminal of a third PMOS, and the second PMOS and the third PMOS share a doping region;
forming a second third gate strip, wherein the second third gate strip is configured to be a gate terminal of the third NMOS, and the second NMOS and the third NMOS share a doping region; and
forming a fourth gate strip, wherein the fourth gate strip is configured to be a co-gate terminal of the fourth PMOS and a fourth NMOS, the third PMOS and the fourth PMOS share a doping region, and the third NMOS and the fourth NMOs share a doping region.

### Claim 17 (depends on 16)

The manufacturing method of claim 16, wherein the doping region shared by the second PMOS and the third PMOS is directed to a first voltage source, and the doping region shared by the second NMOS and the third NMOS is directed to a second voltage source.

### Claim 18 (depends on 16)

The manufacturing method of claim 16, wherein a source terminal of the first PMOS and a source terminal of the fourth PMOS is directed to a first voltage source, and a source terminal of the first NMOS and a source terminal of the fourth terminal are directed to a second voltage source.

### Claim 19 (depends on 16)

The manufacturing method of claim 16, wherein the first first gate strip is connected to the second third gate to direct to a first signal.

### Claim 20 (depends on 16)

The manufacturing method of claim 16, wherein the second first gate strip is connected to the first third gate to direct to a first signal.