# US 12,224,752 B1 · Clock gating circuit for dual-edge-triggered flip-flops > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,224,752 B1 - Document ID: US12224752B1 - Status: Granted - Kind: B1 - Application number: 18/354,374 - Filed: 2023-07-18 - Published: 2025-01-23 - Granted: 2025-02-11 - Earliest claimed: 2023-07-18 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Yimai Peng; Robert Joseph Vachon; Daniel Yingling; Keith Alan Bowman - Web page: https://patentgrep.com/patent/US12224752B1 ## CPC - H03K 3/0372: {of the primary-secondary type} - H03K 19/0016: {by using a control or a clock signal, e.g. in order to apply power supply} - G06F 1/04: Generating or distributing clock signals or signals derived directly therefrom - G06F 1/08: Clock generators with changeable or programmable clock frequency - H03K 17/005: {with several inputs only} - H03K 19/21: EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical - H03K 3/356147: {using pass gates} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An apparatus, including: a clock gating circuit (CGC), including: a clock gating device configured to selectively gate/pass a selected clock signal based on an enable signal to generate an output clock signal; and a clock selection circuit configured to select a non-complementary clock signal or a complementary clock signal to generate the selected clock signal based on the output clock signal and the non-complementary clock signal or the complementary clock signal. ## Claims ### Claim 1 An apparatus, comprising: a clock gating circuit (CGC), comprising: a clock gating device configured to selectively gate or pass a selected clock signal based on an enable signal to generate an output clock signal; and a clock selection circuit configured to select a non-complementary clock signal or a complementary clock signal to generate a select signal based on the output clock signal and the non-complementary clock signal or the complementary clock signal, and an exclusive-NOR gate including a first input configured to receive the complementary clock signal, a second input configured to receive the select signal from the clock selection circuit, and an output configured to output the selected clock signal based on the select signal. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the clock gating device is configured to pass the selected clock signal based on the enable signal being asserted. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the clock gating device is configured to generate the output clock signal at a fixed logic level based on the enable signal being deasserted. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the fixed logic level is a logic level of the output clock signal at substantially a time when the enable signal becomes deasserted. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the clock selection circuit is configured to select the non-complementary clock signal or the complementary clock in response to the enable signal becoming asserted. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the CGC further comprises a multiplexer including a first input configured to receive the non-complementary clock signal, a second input configured to receive the complementary clock signal, a select input configured to receive a select signal from the clock selection circuit, and an output configured to output the selected clock signal. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the CGC further comprises a multiplexer including a non-inverting input configured to receive the non-complementary clock signal, an inverting input configured to receive and invert the non-complementary clock signal to generate the complementary clock signal, a select input configured to receive a select signal from the clock selection circuit, and an output configured to output the selected clock signal. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the clock gating device comprises a latch including a data input configured to receive the selected clock signal, a clock input configured to receive the enable signal, and a data output configured to output the output clock signal. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the clock gating device comprises: a transmission gate including an input configured to receive the selected clock signal, a complementary control input configured to receive a complementary enable signal, and a non-complementary control input configured to receive a non-complementary enable signal; a latch inverter including an input coupled to an output of the transmission gate; and a latch tristate inverter including an input coupled to an output of the latch inverter, an output coupled to the input of the latch inverter, a complementary control signal configured to receive the non-complementary enable signal, and a non-complementary control signal configured to receive the complementary enable signal. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein the CGC further comprises: a first inverter configured to generate the complementary enable signal based on the enable signal; and a second inverter configured to generate the non-complementary enable signal based on the complementary enable signal. ### Claim 11 (depends on 9) The apparatus of claim 9, wherein the clock gating device further comprises an output inverter coupled to an output of the latch inverter. ### Claim 12 (depends on 1) The apparatus of claim 1, wherein the clock selection circuit comprises a logic level comparator including a first input configured to receive the output clock signal, a second input configured to receive the non-complementary clock signal or the complementary clock signal, and an output configured to output a logic level difference signal, wherein the selection of the non-complementary clock signal or the complementary clock is based on the logic level difference signal. ### Claim 13 (depends on 12) The apparatus of claim 12, wherein the logic level comparator comprises an exclusive-OR gate. ### Claim 14 (depends on 12) The apparatus of claim 12, wherein the clock selection circuit further comprises a latch including a data input coupled to the output of the logic level comparator, a clock input configured to receive the enable signal, and an output configured to generate a select signal to effectuate the selection of the non-complementary clock signal or the complementary clock signal. ### Claim 15 (depends on 12) The apparatus of claim 12, wherein the clock selection circuit comprises: a transmission gate including an input coupled to an output of the logic level comparator, a complementary control input configured to receive a non-complementary enable signal, and a non-complementary control input configured to receive a complementary enable signal; a latch inverter including an input coupled to an output of the transmission gate; and a latch tristate inverter including an input coupled to an output of the latch inverter, an output coupled to the input of the latch inverter, a complementary control signal configured to receive the complementary enable signal, and a non-complementary control signal configured to receive the non-complementary enable signal. ### Claim 16 (depends on 15) The apparatus of claim 15, wherein the CGC further comprises: a first inverter configured to generate the complementary enable signal based on the enable signal; and a second inverter configured to generate the non-complementary enable signal based on the complementary enable signal. ### Claim 17 (depends on 1) The apparatus of claim 1, further comprising a set of one or more dual-edge-triggered flip-flops including a set of one or more clock inputs configured to receive the output clock signal. ### Claim 18 An apparatus, comprising: a clock gating circuit (CGC), comprising: a multiplexer including a first input configured to receive a non-complementary clock signal and a second input configured to receive a complementary clock signal; a clock gating device including a first input coupled to an output of the multiplexer and a second input configured to receive an enable signal, the clock gating device comprising a transmission gate including an input coupled to the output of the multiplexer, a complementary control input configured to receive a complementary enable signal, and a non-complementary control input configured to receive a non-complementary enable signal, a latch inverter including an input coupled to an output of the transmission gate, and a latch tristate inverter including an input coupled to an output of the latch inverter, an output coupled to the input of the latch inverter, a complementary control signal configured to receive the non-complementary enable signal, and a non-complementary control signal configured to receive the complementary enable signal; and a clock selection circuit including a first input coupled to an output of the clock gating device, a second input configured to receive the non-complementary or complementary clock signal, a third input configured to receive the enable signal, and an output coupled to a select input of the multiplexer. ### Claim 19 (depends on 18) The apparatus of claim 18, wherein the clock selection circuit comprises: a logic level comparator including a first input coupled to the output of the clock gating device and a second input configured to receive the non-complementary or complementary clock signal; and a latch including a first input coupled to an output of the logic level comparator, a second input configured to receive the enable signal, and an output coupled to the select input of the multiplexer. ### Claim 20 (depends on 19) The apparatus of claim 19, wherein the logic level comparator comprises a logic gate including the first input coupled to the output of the clock gating device, a second input configured to receive the non-complementary or complementary clock signal, and the output coupled to the first input of the latch. ### Claim 21 (depends on 18) The apparatus of claim 18, wherein the multiplexer comprises an inverter including the first input configured to receive the non-complementary clock signal, a logic gate including the second input coupled to an output of the inverter, the select input coupled to the output of the clock selection circuit, and the output coupled to the clock gating device. ### Claim 22 (depends on 21) The apparatus of claim 21, wherein the logic gate comprises an exclusive-NOR gate.