# US 12,224,749 B2 · Interface circuit, interface circuit protection method, and terminal device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,224,749 B2 - Document ID: US12224749B2 - Status: Granted - Kind: B2 - Application number: 18/043,215 - Filed: 2021-07-29 - Published: 2024-01-25 - Granted: 2025-02-11 - Earliest claimed: 2020-08-31 - Assignees: Huawei Technologies Co., Ltd. - Applicants: Huawei Technologies Co., Ltd. - Inventors: Ting Huang; Chen Zhu; Yingqun Feng - Web page: https://patentgrep.com/patent/US12224749B2 ## CPC - H03K 19/017509: {Interface arrangements} - H03K 19/018507: {Interface arrangements} - G06F 13/385: {for adaptation of a particular data processing system to different peripheral devices} - H02J 7/80: including monitoring or indicating arrangements - H03K 19/003: Modifications for increasing the reliability {for protection} - H03K 19/017581: {programmable} - H03K 19/018585: {programmable} - H02J 2207/30: Charge provided using DC bus or data bus of a computer - H04R 3/00: Circuits for transducers (arrangements for producing a reverberation or echo sound G10K15/08; amplifiers H03F) - H04R 2420/09: Applications of special connectors, e.g. USB, XLR, in loudspeakers, microphones or headphones - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H02J: ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY - H04R: LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; ELECTRIC HEARING AIDS; PUBLIC ADDRESS SYSTEMS (producing sounds with frequency not determined by supply frequency G10K) ## Abstract This disclosure provides example interface circuits, interface circuit protection methods, and terminal devices. An example interface circuit includes a switching unit, a power input end, a first function pin, a second function pin, a control signal input end, a detection port, a grounding output end, a first resistor, a second resistor, a third resistor, a fourth resistor, and an on-off apparatus. The switching unit includes a wire grounding GND end, a circuit power supply Vcc end, a first switch circuit, and a second switch circuit. The on-off apparatus includes an input pin, a first on-off pin, and a second on-off pin. The switching unit is configured to switch, in response to a control signal that is input through the control signal input end, functions corresponding to the first function pin and the second function pin. ## Claims ### Claim 1 An interface circuit, wherein the interface circuit comprises a switching unit, a power input end, a first function pin, a second function pin, a control signal input end, a detection port, a grounding output end, a first resistor, a second resistor, a third resistor, a fourth resistor, and an on-off apparatus; the switching unit comprises a wire grounding GND end, a circuit power supply Vcc end, a first switch circuit, and a second switch circuit, wherein the first switch circuit comprises a first input end, a second input end, a first control end, and a first output end, and the second switch circuit comprises a third input end, a fourth input end, a second control end, and a second output end; the first output end is connected to the first function pin, and the second output end is connected to the second function pin; the first resistor is connected in series between the circuit power supply Vcc end and the power input end; one end of the second resistor is connected to the wire grounding GND end, and the other end of the second resistor is grounded; one end of the third resistor is connected to the control signal input end, and the other end of the third resistor is connected to the first control end and the second control end; one end of the fourth resistor is connected to the detection port, and the other end of the fourth resistor is connected to the first input end and the third input end; the on-off apparatus comprises an input pin, a first on-off pin, and a second on-off pin; the input pin is connected to the power input end; the first on-off pin is separately connected to the second input end and the fourth input end; the second on-off pin is grounded and connected to the grounding output end; when the input pin inputs a low level, the first on-off pin is disconnected from the second on-off pin; when the input pin inputs a high level, the first on-off pin is connected from the second on-off pin; and the switching unit is configured to switch, in response to a control signal that is input through the control signal input end, functions corresponding to the first function pin and the second function pin. ### Claim 2 (depends on 1) The interface circuit according to claim 1, wherein the switching unit is a switch chip, and the switch chip comprises a Vcc pin, a GND pin, a first common pin, a second common pin, a first input pin, a second input pin, a first normally-open pin, a second normally-open pin, a first normally-closed pin, and a second normally-closed pin, wherein: the circuit power supply Vcc end is the Vcc pin, the wire grounding GND end is the GND pin, the first input end is the first normally-open pin, the second input end is the second normally-open pin, the third input end is the second normally-closed pin, the fourth input end is the first normally-closed pin, the first control end is the first input pin, the second control end is the second input pin, the first output end is the first common pin, and the second output end is the second common pin. ### Claim 3 (depends on 1) The interface circuit according to claim 1, wherein the on-off apparatus is an NMOS transistor; and wherein: a gate of the NMOS transistor is the input pin, a drain of the NMOS transistor is the first on-off pin, and a source of the NMOS transistor is the second on-off pin. ### Claim 4 (depends on 1) The interface circuit according to claim 1, wherein the on-off apparatus is a PMOS transistor; and wherein: a gate of the PMOS transistor is the input pin, a source of the PMOS transistor is the first on-off pin, and a drain of the PMOS transistor is the second on-off pin. ### Claim 5 (depends on 1) The interface circuit according to claim 1, wherein a resistance value of the fourth resistor is from 100 ohms to 300 ohms. ### Claim 6 (depends on 1) The interface circuit according to claim 1, wherein the interface circuit comprises a universal serial bus Type-c interface, the first function pin is a first sideband use SBU pin of the universal serial bus Type-c interface, and the second function pin is a second sideband use SBU pin of the universal serial bus Type-c interface. ### Claim 7 (depends on 1) The interface circuit according to claim 1, wherein the interface circuit further comprises a first filter capacitor, and the circuit power supply Vcc end is grounded through the first filter capacitor. ### Claim 8 (depends on 1) The interface circuit according to claim 1, wherein the interface circuit further comprises a second filter capacitor, one end of the second filter capacitor is connected to the input pin, and the other end of the second filter capacitor is connected to the first on-off pin. ### Claim 9 (depends on 1) An interface circuit protection method, wherein the interface circuit protection method is applied to the interface circuit according to claim 1, and the interface circuit protection method comprises: detecting a type of a device accessing the interface circuit; and in response to determining that the type of the device is a charging device, outputting a low level to a circuit power supply Vcc end of the interface circuit. ### Claim 10 A terminal device, wherein the terminal device comprises an interface circuit; wherein the interface circuit comprises a switching unit, a power input end, a first function pin, a second function pin, a control signal input end, a detection port, a grounding output end, a first resistor, a second resistor, a third resistor, a fourth resistor, and an on-off apparatus; the switching unit comprises a wire grounding GND end, a circuit power supply Vcc end, a first switch circuit, and a second switch circuit, wherein the first switch circuit comprises a first input end, a second input end, a first control end, and a first output end, and the second switch circuit comprises a third input end, a fourth input end, a second control end, and a second output end; the first output end is connected to the first function pin, and the second output end is connected to the second function pin; the first resistor is connected in series between the circuit power supply Vcc end and the power input end; one end of the second resistor is connected to the wire grounding GND end, and the other end of the second resistor is grounded; one end of the third resistor is connected to the control signal input end, and the other end of the third resistor is connected to the first control end and the second control end; one end of the fourth resistor is connected to the detection port, and the other end of the fourth resistor is connected to the first input end and the third input end; the on-off apparatus comprises an input pin, a first on-off pin, and a second on-off pin; the input pin is connected to the power input end; the first on-off pin is separately connected to the second input end and the fourth input end; the second on-off pin is grounded and connected to the grounding output end; when the input pin inputs a low level, the first on-off pin is disconnected from the second on-off pin; when the input pin inputs a high level, the first on-off pin is connected from the second on-off pin; and the switching unit is configured to switch, in response to a control signal that is input through the control signal input end, functions corresponding to the first function pin and the second function pin. ### Claim 11 (depends on 10) The terminal device according to claim 10, wherein the switching unit is a switch chip, and the switch chip comprises a Vcc pin, a GND pin, a first common pin, a second common pin, a first input pin, a second input pin, a first normally-open pin, a second normally-open pin, a first normally-closed pin, and a second normally-closed pin, wherein: the circuit power supply Vcc end is the Vcc pin, the wire grounding GND end is the GND pin, the first input end is the first normally-open pin, the second input end is the second normally-open pin, the third input end is the second normally-closed pin, the fourth input end is the first normally-closed pin, the first control end is the first input pin, the second control end is the second input pin, the first output end is the first common pin, and the second output end is the second common pin. ### Claim 12 (depends on 10) The terminal device according to claim 10, wherein the on-off apparatus is an NMOS transistor; and wherein: a gate of the NMOS transistor is the input pin, a drain of the NMOS transistor is the first on-off pin, and a source of the NMOS transistor is the second on-off pin. ### Claim 13 (depends on 11) The terminal device according to claim 11, wherein the on-off apparatus is an NMOS transistor; and wherein: a gate of the NMOS transistor is the input pin, a drain of the NMOS transistor is the first on-off pin, and a source of the NMOS transistor is the second on-off pin. ### Claim 14 (depends on 10) The terminal device according to claim 10, wherein the on-off apparatus is a PMOS transistor; and wherein: a gate of the PMOS transistor is the input pin, a source of the PMOS transistor is the first on-off pin, and a drain of the PMOS transistor is the second on-off pin. ### Claim 15 (depends on 11) The terminal device according to claim 11, wherein the on-off apparatus is a PMOS transistor; and wherein: a gate of the PMOS transistor is the input pin, a source of the PMOS transistor is the first on-off pin, and a drain of the PMOS transistor is the second on-off pin. ### Claim 16 (depends on 10) The terminal device according to claim 10, wherein a resistance value of the fourth resistor is from 100 ohms to 300 ohms. ### Claim 17 (depends on 10) The terminal device according to claim 10, wherein the interface circuit comprises a universal serial bus Type-c interface, the first function pin is a first sideband use SBU pin of the universal serial bus Type-c interface, and the second function pin is a second sideband use SBU pin of the universal serial bus Type-c interface. ### Claim 18 (depends on 11) The terminal device according to claim 11, wherein the interface circuit comprises a universal serial bus Type-c interface, the first function pin is a first sideband use SBU pin of the universal serial bus Type-c interface, and the second function pin is a second sideband use SBU pin of the universal serial bus Type-c interface. ### Claim 19 (depends on 10) The terminal device according to claim 10, wherein the interface circuit further comprises a first filter capacitor, and the circuit power supply Vcc end is grounded through the first filter capacitor. ### Claim 20 (depends on 10) The terminal device according to claim 10, wherein the interface circuit further comprises a second filter capacitor, one end of the second filter capacitor is connected to the input pin, and the other end of the second filter capacitor is connected to the first on-off pin.