# US 12,224,747 B2 · Semiconductor device related to calibrating termination resistance > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,224,747 B2 - Document ID: US12224747B2 - Status: Granted - Kind: B2 - Application number: 18/343,537 - Filed: 2023-06-28 - Published: 2023-10-26 - Granted: 2025-02-11 - Earliest claimed: 2022-04-19 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Chae Sung Lim; Jung Taek You; Saeng Hwan Kim; Sang Sic Yoon; Hong Joo Song - Web page: https://patentgrep.com/patent/US12224747B2 ## CPC - H03K 19/0005: {Modifications of input or output impedance} - G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers - G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load} - G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device} - G11C 29/022: {in I/O circuitry} - G11C 29/028: {with adaption or trimming of parameters} - G11C 29/50008: {of impedance} - G11C 2207/2254: Calibration - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor system includes a controller configured to apply a command address, a first chip selection signal, and a second chip selection signal, and a semiconductor device including a first rank and a second rank configured to calibrate each termination resistance, based on the command address, the first chip selection signal, and the second chip selection signal. ## Claims ### Claim 1 A semiconductor system comprising: a controller configured to transmit a command address, a first chip selection signal, and a second chip selection signal; and a semiconductor device configured to receive the command address, the first chip selection signal, and the second chip selection signal, the semiconductor device including a first rank and a second rank that are configured to calibrate each termination resistance, based on the command address, the first chip selection signal, and the second chip selection signal, wherein the first rank calibrates the termination resistance of the first rank to a target resistance, based on the command address and the first chip selection signal when a write operation on the first rank is performed, and wherein the second rank calibrates the termination resistance of the second rank to a dynamic resistance, based on the command address and the second chip selection signal when a write operation on the second rank is performed. ### Claim 2 (depends on 1) The semiconductor system of claim 1, wherein the first rank calibrates the termination resistance of the first rank to the target resistance when a write command is input through the command address in a state in which the first chip selection signal is set to have a first voltage level. ### Claim 3 (depends on 2) The semiconductor system of claim 2, wherein the second rank calibrates the termination resistance of the second rank to the dynamic resistance according to the second chip selection signal set to have a second voltage level when the write operation on the first rank is performed. ### Claim 4 (depends on 3) The semiconductor system of claim 3, wherein the second voltage level is set to be higher than the first voltage level. ### Claim 5 (depends on 3) The semiconductor system of claim 3, wherein the first voltage level is set to a voltage level substantially half of a supply voltage, and wherein the second voltage level is set to a voltage level of substantially the supply voltage. ### Claim 6 (depends on 2) The semiconductor system of claim 2, wherein the second rank calibrates the termination resistance of the second rank to the dynamic resistance during a burst section that is set based on the number of occurrences of a pulse of the second chip selection signal set to have the second voltage level when the write operation on the first rank is performed. ### Claim 7 (depends on 1) The semiconductor system of claim 1, wherein the second rank calibrates the termination resistance of the second rank to the target resistance, based on the command address and the second chip selection signal when a write operation on the second rank is performed, and wherein the first rank calibrates the termination resistance of the first rank to the dynamic resistance, based on the first chip selection signal when the write operation on the second rank is performed. ### Claim 8 (depends on 7) The semiconductor system of claim 7, wherein the second rank calibrates the termination resistance of the second rank to the target resistance when a write command is input through the command address in a state in which the second chip selection signal set to a first voltage level is generated. ### Claim 9 (depends on 8) The semiconductor system of claim 8, wherein the first rank calibrates the termination resistance of the first rank to the dynamic resistance according to first chip selection signal set to a second voltage level when the write operation on the second rank is performed. ### Claim 10 (depends on 9) The semiconductor system of claim 9, wherein the second voltage level is set to be higher than the first voltage level, wherein the first voltage level is set to a voltage level substantially half of a supply voltage, and wherein the second voltage level is set to a voltage level of substantially the supply voltage. ### Claim 11 (depends on 7) The semiconductor system of claim 7, wherein the first rank calibrates the termination resistance of the first rank during a burst section that is set based on the number of occurrences of a pulse of the first chip selection signal set to a second voltage level when the write operation on the second rank is performed. ### Claim 12 (depends on 1) The semiconductor system of claim 1, wherein the controller is configured to: generate the first chip selection signal driven at a first voltage level and the second chip selection signal driven at a second voltage level when the write operation on the first rank is performed, and generate the second chip selection signal driven at the first voltage level and the first chip selection signal driven at the second voltage level when a write operation on the second rank is performed. ### Claim 13 (depends on 1) The semiconductor system of claim 1, wherein the controller includes: a first chip selection signal generation circuit configured to generate the first chip selection signal driven at a first voltage level when the write operation on the first rank is performed, and to generate the first chip selection signal driven at a second voltage level when a write operation on the second rank is performed; and a second chip selection signal generation circuit configured to generate the second chip selection signal driven at the first voltage level when the write operation on the second rank is performed, and to generate the second chip selection signal driven at the second voltage level when the write operation on the first rank is performed. ### Claim 14 (depends on 13) The semiconductor system of claim 13, wherein the first chip selection signal generation circuit is configured to: pull-up drive the first chip selection signal, based at least one pull-up signal, and pull-down drive the first chip selection signal, based on at least one pull-down signal. ### Claim 15 (depends on 1) The semiconductor system of claim 1, wherein the first rank includes: a first command control signal generation circuit configured to generate a first command control signal that is activated when the write operation on the first rank is performed based on the command address and the first chip selection signal; a first dynamic control signal generation circuit configured to generate a first dynamic control signal when a write operation on the second rank is performed based on the first chip selection signal; and a first termination control circuit configured to generate a first termination resistance calibration signal for calibrating the termination resistance of the first rank, based on the first command control signal and the first dynamic control signal. ### Claim 16 (depends on 15) The semiconductor system of claim 15, wherein the second rank includes: a second command control signal generation circuit configured to generate a second command control signal that is activated when the write operation on the second rank is performed based on the command address and the second chip selection signal; a second dynamic control signal generation circuit configured to generate a second dynamic control signal when the write operation on the first rank is performed based on the second chip selection signal; and a second termination control circuit configured to generate a second termination resistance calibration signal for calibrating the termination resistance of the second rank, based on the second command control signal and the second dynamic control signal. ### Claim 17 A semiconductor device comprising: a first rank configured to calibrate a first termination resistance to a target resistance when a write command is input through a command address in a state in which a first chip selection signal set to have a first voltage level is generated; and a second rank configured to calibrate a second termination resistance to a target resistance when the write command is input through the command address in a state in which a second chip selection signal set to have a first voltage level is generated, wherein the second rank calibrates the second termination resistance to the dynamic resistance according to the second chip selection signal set to have the second voltage level when a write operation on the first rank is performed. ### Claim 18 (depends on 17) The semiconductor device of claim 17, wherein the second voltage level is set to be higher than the first voltage level, wherein the first voltage level is set to a voltage level substantially half of a supply voltage, and wherein the second voltage level is set to a voltage level of substantially the supply voltage. ### Claim 19 (depends on 17) The semiconductor device of claim 17, wherein the second rank calibrates the second termination resistance to the dynamic resistance during a burst section that is set based on the number of occurrences of a pulse of the second chip selection signal set to have the second voltage level when the write operation on the first rank is performed. ### Claim 20 (depends on 17) The semiconductor device of claim 17, wherein the first rank calibrates the first termination resistance to the dynamic resistance according to the first chip selection signal set to have the second voltage level when a write operation on the second rank is performed. ### Claim 21 (depends on 17) The semiconductor device of claim 17, wherein the first rank calibrates the first termination resistance to the dynamic resistance during a burst section that is set based on the number of occurrences of a pulse of the first chip selection signal set to have the second voltage level when a write operation on the second rank is performed. ### Claim 22 A semiconductor system comprising: a controller configured to transmit a command address, a first chip selection signal, a second chip selection signal, and a third chip selection signal; and a semiconductor device configured to receive the command address, the first chip selection signal, the second chip selection signal, and the third chip selection signal, the semiconductor device including a first rank, a second rank, and a third rank that are configured to calibrate each termination resistance, based on the command address, the first chip selection signal, the second chip selection signal, and the third chip selection signal, wherein the first rank calibrates the termination resistance of the first rank to a target resistance, based on the command address and the first chip selection signal when a write operation on the first rank is performed, wherein the second rank calibrates the termination resistance of the second rank to a first dynamic resistance, based on the second chip selection signal when the write operation on first second rank is performed, and wherein the third rank calibrates the termination resistance of the third rank to a second dynamic resistance, based on the third chip selection signal when the write operation on the first rank is performed. ### Claim 23 (depends on 22) The semiconductor system of claim 22, wherein the first rank calibrates the termination resistance of the first rank to the target resistance when a write command is input through the command address in a state in which the first chip selection signal set to have a first voltage level is generated. ### Claim 24 (depends on 23) The semiconductor system of claim 23, wherein the second rank calibrates the termination resistance of the second rank to the first dynamic resistance according to the second chip selection signal set to have a second voltage level when the write operation on the first rank is performed. ### Claim 25 (depends on 24) The semiconductor system of claim 24, wherein the third rank calibrates the termination resistance of the third rank to the second dynamic resistance according to the third chip selection signal set to have the second voltage level when the write operation on the first rank is performed. ### Claim 26 (depends on 25) The semiconductor system of claim 25, wherein the second voltage level is set to be higher than the first voltage level, and wherein the third voltage level is set to be higher than the second voltage level.