# US 12,224,741 B2 · Control circuit with bias circuitry for a semiconductor memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,224,741 B2 - Document ID: US12224741B2 - Status: Granted - Kind: B2 - Application number: 17/935,811 - Filed: 2022-09-27 - Published: 2023-01-26 - Granted: 2025-02-11 - Earliest claimed: 2022-03-25 - Assignees: Changxin Memory Technologies, Inc. - Applicants: Changxin Memory Technologies, Inc. - Inventors: Yupeng Fan - Web page: https://patentgrep.com/patent/US12224741B2 ## CPC - H03K 17/6871: {the output circuit comprising more than one controlled field-effect transistor} - G06F 1/3203: Power management, i.e. event-based initiation of a power-saving mode - G11C 5/148: {Details of power up or power down circuits, standby circuits or recovery circuits} - G11C 7/109: {Control signal input circuits} - G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device} - G11C 7/225: {Clock input buffers} - G11C 8/06: Address interface arrangements, e.g. address buffers - G11C 11/34: using semiconductor devices - G11C 11/401: forming cells needing refreshing or charge regeneration, i.e. dynamic cells - G11C 11/4072: Circuits for initialization, powering up or down, clearing memory or presetting - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - G11C 11/4082: {Address Buffers; level conversion circuits} - G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers - H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) - G11C 2207/2227: Standby or low power modes - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A control circuit includes a bias circuit. The bias circuit is configured to provide a bias current for a functional circuit. The bias circuit includes a first bias circuit and a second bias circuit. The first bias circuit is configured to provide a first bias current, and the second bias circuit is configured to provide a second bias current. Herein, the first bias current is smaller than the second bias current, the first bias circuit is configured to be in a normally open state after being powered on, and the second bias circuit is configured to receive a bias enabling signal and provide the second bias current based on the bias enabling signal. ## Claims ### Claim 1 A control circuit, comprising a bias circuit, the bias circuit being configured to provide a bias current for a functional circuit, the bias circuit comprising a first bias circuit and a second bias circuit, the first bias circuit being configured to provide a first bias current, and the second bias circuit being configured to provide a second bias current, wherein the first bias current is smaller than the second bias current, the first bias circuit is configured to be in a normally open state after being powered on, and the second bias circuit is configured to receive a bias enabling signal and provide the second bias current based on the bias enabling signal; wherein the functional circuit is configured to receive an excitation signal and to be started based on the excitation signal, wherein a time point when the functional circuit receives the excitation signal is later than a time point when the bias circuit receives the bias enabling signal; and wherein the control circuit further comprising an enabling circuit, wherein the enabling circuit is configured to receive a power switching signal and output the bias enabling signal and the excitation signal based on the power switching signal, wherein the power switching signal characterizes starting the functional circuit. ### Claim 2 (depends on 1) The control circuit of claim 1, wherein the power switching signal comprises a preceding first changing edge and a subsequent second changing edge, and the enabling circuit is further configured to output the bias enabling signal at the first changing edge, and configured to output the excitation signal at the second changing edge. ### Claim 3 (depends on 2) The control circuit of claim 2, wherein a changing direction of the first changing edge is opposite to a changing direction of the second changing edge. ### Claim 4 (depends on 2) The control circuit of claim 2, wherein the first changing edge is switched from a low level state to a high level state, and the second changing edge is switched from a high level state to a low level state. ### Claim 5 (depends on 1) The control circuit of claim 1, wherein the enabling circuit is further configured to receive a state signal, perform logical operation processing based on the power switching signal and the state signal, and output the bias enabling signal and the excitation signal, wherein the state signal characterizes that the control circuit is in a Power Down State or a Power On State. ### Claim 6 (depends on 5) The control circuit of claim 5, wherein the enabling circuit comprises a first logic circuit and a second logic circuit, wherein the first logic circuit is configured to receive the power switching signal and the state signal, and perform first logic operation on the power switching signal and the state signal to output the bias enabling signal, and the second logic circuit being configured to receive the power switching signal and the state signal, and perform second logic operation on the power switching signal and the state signal to output the excitation signal. ### Claim 7 (depends on 6) The control circuit of claim 6, wherein the first logic circuit comprises a first NOR gate, a second NOR gate and a first NOT gate, wherein one input end of the first NOR gate is configured to receive the power switching signal, the other input end of the first NOR gate is connected with an output end of the second NOR gate, one input end of the second NOR gate is connected with an output end of the first NOR gate, the other input end of the second NOR gate is configured to receive the state signal, and the output end of the second NOR gate is also connected with an input end of the first NOT gate. ### Claim 8 (depends on 6) The control circuit of claim 6, wherein the second logic circuit comprises a second NOT gate, a first NAND gate, a second NAND gate and a third NOT gate, wherein an input end of the second NOT gate is configured to receive the state signal, an output end of the second NOT gate is connected with one input end of the first NAND gate, the other input end of the first NAND gate is connected with an output end of the second NAND gate, an output end of the first NAND gate is connected with one input end of the second NAND gate, the other input end of the second NAND gate is configured to receive the power switching signal, and the output end of the first NAND gate is also connected with an input end of the third NOT gate. ### Claim 9 A control circuit, comprising a bias circuit, the bias circuit being configured to provide a bias current for a functional circuit, the bias circuit comprising a first bias circuit and a second bias circuit, the first bias circuit being configured to provide a first bias current, and the second bias circuit being configured to provide a second bias current, wherein the first bias current is smaller than the second bias current, the first bias circuit is configured to be in a normally open state after being powered on, and the second bias circuit is configured to receive a bias enabling signal and provide the second bias current based on the bias enabling signal; wherein the functional circuit comprises an input buffer circuit. ### Claim 10 (depends on 9) The control circuit of claim 9, wherein the first bias circuit is connected in parallel with the second bias circuit, the first bias circuit comprises a first bias resistor, and the second bias circuit comprises a second bias resistor, wherein a resistance value of the first bias resistor is greater than a resistance value of the second bias resistor. ### Claim 11 (depends on 10) The control circuit of claim 10, wherein the first bias circuit further comprises a first transistor, a second transistor, a third transistor and a fourth transistor, wherein a drain electrode of the first transistor and a drain electrode of the second transistor are both connected with a power supply terminal, a gate electrode of the first transistor and a gate electrode of the second transistor are both connected with a ground terminal, a source electrode of the first transistor is connected with a drain electrode of the third transistor, a source electrode of the second transistor is connected with a drain electrode of the fourth transistor, a gate electrode of the third transistor and a gate electrode of the fourth transistor are both connected with a source electrode of the third transistor, the source electrode of the third transistor is connected with the ground terminal through the first bias resistor, and a source electrode of the fourth transistor is connected with the functional circuit, and configured to provide the first bias current for the functional circuit. ### Claim 12 (depends on 10) The control circuit of claim 10, wherein the second bias circuit further comprises a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor, wherein a drain electrode of the fifth transistor and a drain electrode of the sixth transistor are both connected with a power supply terminal, a gate electrode of the fifth transistor and a gate electrode of the sixth transistor are both connected with the bias enabling signal, a source electrode of the fifth transistor is connected with a drain electrode of the seventh transistor, a source electrode of the sixth transistor is connected with a drain electrode of the eighth transistor, a gate electrode of the seventh transistor and a gate electrode of the eighth transistor are both connected with a source electrode of the seventh transistor, the source electrode of the seventh transistor is connected with the ground terminal through the second bias resistor, and a source electrode of the eighth transistor is connected with the functional circuit, and configured to provide the second bias current for the functional circuit. ### Claim 13 A semiconductor memory, comprising a control circuit, the control circuit comprising a bias circuit, the bias circuit being configured to provide a bias current for a functional circuit, the bias circuit comprising a first bias circuit and a second bias circuit, the first bias circuit being configured to provide a first bias current, and the second bias circuit being configured to provide a second bias current, wherein the first bias current is smaller than the second bias current, the first bias circuit is configured to be in a normally open state after being powered on, and the second bias circuit is configured to receive a bias enabling signal and provide the second bias current based on the bias enabling signal; wherein the functional circuit is configured to receive an excitation signal and to be started based on the excitation signal, wherein a time point when the functional circuit receives the excitation signal is later than a time point when the bias circuit receives the bias enabling signal. ### Claim 14 (depends on 13) The control circuit of claim 13, further comprising an enabling circuit, wherein the enabling circuit is configured to receive a power switching signal and output the bias enabling signal and the excitation signal based on the power switching signal, wherein the power switching signal characterizes starting the functional circuit. ### Claim 15 (depends on 14) The control circuit of claim 14, wherein the power switching signal comprises a preceding first changing edge and a subsequent second changing edge, and the enabling circuit is further configured to output the bias enabling signal at the first changing edge, and configured to output the excitation signal at the second changing edge. ### Claim 16 (depends on 15) The control circuit of claim 15, wherein a changing direction of the first changing edge is opposite to a changing direction of the second changing edge. ### Claim 17 (depends on 15) The control circuit of claim 15, wherein the first changing edge is switched from a low level state to a high level state, and the second changing edge is switched from a high level state to a low level state.