Fractional delay filter for a digital signal processing system

A processing element for implementation in a digital signal processing system, the processing element configured to:

• receive a serial data stream comprising a plurality of time-ordered digital values;
• convert the serial data stream into a plurality of parallel data streams so that the plurality of data streams output a set of the plurality of time-ordered digital values;
• store one or more of the plurality of time-ordered digital values of the set;
• and
• weight each of the time-ordered digital values of the set consistent with a Farrow structured fractional delay filter using the plurality of digital values and one or more previously stored values to produce a plurality of filtered time-ordered digital values.

A digital processing system comprising:

• an analog-to-digital converter configured to receive a first analog signal and convert the first analog signal to a first digital serial data stream comprising a sequence of digital values representing samples of the analog signal;
• a processing element configured to:
• convert the digital serial data stream into a plurality of parallel, time-ordered data streams so that the plurality of data streams output a set of the plurality of time-ordered digital values;
• store one or more of the plurality of time-ordered digital values of the set;
• weight each time-ordered digital value of the set substantially consistent with a Farrow structured fractional delay filter using the plurality of digital values and one or more previously stored values to produce a plurality of filtered time-ordered digital values;
• and
• a digital-to-analog converter configured to convert the plurality of filtered time-ordered digital values into a second analog signal.