# US 12,224,713 B2 · Multiple-stage Doherty power amplifiers implemented with multiple semiconductor technologies > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,224,713 B2 - Document ID: US12224713B2 - Status: Granted - Kind: B2 - Application number: 17/360,821 - Filed: 2021-06-28 - Published: 2022-12-29 - Granted: 2025-02-11 - Earliest claimed: 2021-06-28 - Assignees: NXP USA, Inc. - Applicants: NXP USA, Inc. - Inventors: Mark Pieter van der Heijden; Joseph Staudinger; Elie A. Maalouf - Web page: https://patentgrep.com/patent/US12224713B2 ## CPC - H03F 1/0288: {using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers} - H03F 1/22: by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively - H03F 3/195: in integrated circuits - H03F 3/211: {using a combination of several amplifiers (H03F3/60 takes precedence)} - H03F 3/213: in integrated circuits - H03F 3/24: of transmitter output stages - H10W 44/20: at high-frequency [HF] or radio frequency [RF] - H03F 2200/402: A series resonance being added in shunt in the output circuit, e.g. base, gate, of an amplifier stage - H03F 2200/42: the input to the amplifier being made by capacitive coupling means - H03F 2200/451: the amplifier being a radio frequency amplifier - H03F 2200/48: the output of the amplifier being coupled out by a capacitor - H03F 2200/54: Two or more capacitor coupled amplifier stages in cascade - H03F 2200/75: the amplifier stage being a common source configuration MOSFET - H10W 44/226: {for HF amplifiers} - H03F: AMPLIFIERS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A device includes an integrated circuit (IC) die. The IC die includes a silicon germanium (SiGe) substrate, a first RF signal input terminal, a first RF signal output terminal, a first amplification path between the first RF signal input terminal and the first RF signal output terminal, a second RF signal input terminal, a second RF signal output terminal, and a second amplification path between the second RF signal input terminal and the second RF signal output terminal. The device includes a first power transistor die including a first input terminal electrically connected to the first RF signal output terminal and a second power transistor die including a second input terminal electrically connected to the second RF signal output terminal. The first amplification path can include two heterojunction bipolar transistors (HBTs) connected in a cascode configuration and the second amplification path can include two HBTs connected in a cascode configuration. ## Claims ### Claim 1 An amplifier, comprising: a substrate with a mounting surface; a first power transistor die coupled to the mounting surface, wherein the first power transistor die includes a first III-V semiconductor substrate, a first radio frequency (RF) signal input terminal, a first RF signal output terminal, and a first transistor, wherein the first transistor has a first control terminal electrically coupled to the first RF signal input terminal, and a first current-carrying terminal electrically coupled to the first RF signal output terminal; a second power transistor die coupled to the mounting surface, wherein the second power transistor die includes a second III-V semiconductor substrate, a second radio frequency (RF) signal input terminal, a second RF signal output terminal, and a second transistor, wherein the second transistor has a second control terminal electrically coupled to the first RF signal input terminal, and a second current-carrying terminal electrically coupled to the first RF signal output terminal; a third die coupled to the mounting surface, the third die includes at least one of silicon germanium (SiGe), gallium arsenide (GaAs), and indium phosphide (InP), a third RF signal input terminal, a third RF signal output terminal that is electrically connected to the first RF signal input terminal, a first amplification path between the third RF signal input terminal and the third RF signal output terminal, a fourth RF signal input terminal, a fourth RF signal output terminal that is electrically connected to the second RF signal input terminal, and a second amplification path between the fourth RF signal input terminal and the fourth RF signal output terminal, wherein the first amplification path includes a first heterojunction bipolar transistor (HBT) coupled between the third RF signal input terminal and the third RF signal output terminal and the second amplification path includes a second HBT coupled between the fourth RF signal input terminal and the fourth RF signal output terminal, wherein a first bias control circuit is coupled to a first base of the first HBT and a second bias control circuit is coupled to a second base of the second HBT, and wherein the third die includes a first variable capacitance, a first terminal of the first variable capacitance is electrically connected to a collector of the second HBT, and a second terminal of the first variable capacitance is electrically connected to the base of the first HBT; and a first connection electrically coupled between the second RF signal output terminal and the first RF signal output terminal. ### Claim 2 (depends on 1) The amplifier of claim 1, wherein the first amplification path includes a third HBT coupled between the third RF signal input terminal and the third RF signal output terminal and the first HBT and the third HBT are connected in a cascode configuration and the second amplification path includes a fourth HBT coupled between the fourth RF signal input terminal and the fourth RF signal output terminal and the second HBT and the fourth HBT are connected in a cascode configuration. ### Claim 3 (depends on 2) The amplifier of claim 2, wherein the second amplification path includes a first variable capacitance, a first terminal of the first variable capacitance is electrically connected to a collector terminal of the fourth HBT, and a second terminal of the first variable capacitance is electrically connected to a base terminal of the second HBT. ### Claim 4 (depends on 2) The amplifier of claim 2, wherein the first amplification path includes a second variable capacitance, a first terminal of the second variable capacitance is electrically connected to a collector terminal of the third HBT, and a second terminal of the second variable capacitance is electrically connected to a base terminal of the first HBT. ### Claim 5 (depends on 1) The amplifier of claim 1, wherein the first amplification path extends in a first direction in the third die and the second amplification path extends in a second direction in the third die, and the first direction is rotationally offset from the second direction by 90 degrees. ### Claim 6 (depends on 1) The amplifier of claim 1, wherein the first power transistor die is a carrier amplifier die of a Doherty power amplifier, and the second power transistor die is a peaking amplifier die of the Doherty power amplifier. ### Claim 7 (depends on 1) The amplifier of claim 1, wherein the first III-V semiconductor substrate includes gallium nitride and the second III-V semiconductor substrate includes gallium nitride. ### Claim 8 An amplifier, comprising: a first radio frequency (RF) input terminal; a first driver amplifier module including a second RF input terminal electrically connected to the first RF input terminal, a first RF output terminal, and a first driver amplifier, wherein the first driver amplifier includes a first heterojunction bipolar transistor (HBT) a second HBT, and a bias control circuit, wherein the first HBT is coupled to the second HBT in a cascode configuration and wherein the bias control circuit is coupled to a base of the first HBT, and wherein the first driver amplifier includes a first variable capacitance, a first terminal of the first variable capacitance is electrically connected to a collector of the second HBT, and a second terminal of the first variable capacitance is electrically connected to the base of the first HBT; and a first power amplifier module including a third RF input terminal electrically connected to the first RF output terminal, a second RF output terminal, and a first power transistor coupled between the third RF input terminal and the second RF output terminal. ### Claim 9 (depends on 8) The amplifier of claim 8, wherein the first driver amplifier module includes at least one of silicon germanium (SiGe), gallium arsenide (GaAs), and indium phosphide (InP). ### Claim 10 (depends on 9) The amplifier of claim 9, wherein the first power amplifier module includes a III-V semiconductor material. ### Claim 11 (depends on 8) The amplifier of claim 8, further comprising: a fourth RF input terminal; a second driver amplifier module including a fifth RF input terminal electrically connected to the fourth RF input terminal, a third RF output terminal, and a second driver amplifier, wherein the second driver amplifier includes a third HBT and a fourth HBT, and the third HBT is coupled to the fourth HBT in a cascode configuration; and a second power amplifier module including a sixth RF input terminal electrically connected to the third RF output terminal, a fourth RF output terminal, and a second power transistor coupled between the sixth RF input terminal and the fourth RF output terminal, wherein the fourth RF output terminal is electrically connected to the second RF output terminal through an impedance inversion element. ### Claim 12 (depends on 11) The amplifier of claim 11, wherein the first driver amplifier module and the second driver amplifier module are in the same integrated circuit die. ### Claim 13 (depends on 12) The amplifier of claim 12, wherein the first driver amplifier module is rotationally offset from the second driver amplifier module by 90 degrees. ### Claim 14 A device, comprising: an integrated circuit (IC) die, wherein the IC die includes a silicon germanium (SiGe) substrate, a first RF signal input terminal, a first RF signal output terminal, a first amplification path between the first RF signal input terminal and the first RF signal output terminal, a second RF signal input terminal, a second RF signal output terminal, and a second amplification path between the second RF signal input terminal and the second RF signal output terminal, wherein the first amplification path includes a first heterojunction bipolar transistor (HBT) coupled between the first RF signal input terminal and the first RF signal output terminal, the second amplification path includes a second heterojunction bipolar transistor (HBT) coupled between the second RF signal input terminal and the second RF signal output terminal, wherein a first bias control circuit is coupled to a first base of the first HBT, and wherein a second bias control circuit is coupled to a second base of the second HBT, and wherein the IC die includes a first variable capacitance, a first terminal of the first variable capacitance is electrically connected to a collector of the second HBT, and a second terminal of the first variable capacitance is electrically connected to the base of the first HBT; a first power transistor die connected between the RF signal input terminal and the first RF signal output terminal; and a second power transistor die connected between the second RF signal input terminal and the second RF signal output terminal. ### Claim 15 (depends on 14) The device of claim 14, wherein the first amplification path includes a third HBT coupled between the first RF signal input terminal and the first RF signal output terminal and the first HBT and the third HBT are connected in a cascode configuration and the second amplification path includes a fourth HBT coupled between the second RF signal input terminal and the second RF signal output terminal and the second HBT and the fourth HBT are connected in a cascode configuration. ### Claim 16 (depends on 15) The device of claim 15, wherein the second amplification path includes a first variable capacitance, a first terminal of the first variable capacitance is electrically connected to a collector terminal of the fourth HBT, and a second terminal of the first variable capacitance is electrically connected to a base terminal of the second HBT. ### Claim 17 (depends on 16) The device of claim 16, wherein the first amplification path includes a second variable capacitance, a first terminal of the second variable capacitance is electrically connected to a collector terminal of the third HBT, and a second terminal of the second variable capacitance is electrically connected to a base terminal of the first HBT. ### Claim 18 (depends on 14) The device of claim 14, wherein the first amplification path extends in a first direction in the IC die and the second amplification path extends in a second direction in the IC die, and the first direction is rotationally offset from the second direction by 90 degrees. ### Claim 19 (depends on 8) The amplifier of claim 8, wherein the bias control circuit is configured to control a small signal gain of the first driver amplifier. ### Claim 20 (depends on 8) The amplifier of claim 8, wherein the first variable capacitance is configured to control a gain slope of the first driver amplifier.