# US 12,224,664 B2 · Gate controller for a charge pump converter > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,224,664 B2 - Document ID: US12224664B2 - Status: Granted - Kind: B2 - Application number: 17/770,094 - Filed: 2020-11-05 - Published: 2022-12-08 - Granted: 2025-02-11 - Earliest claimed: 2019-11-05 - Assignees: EM Microelectronic-Marin SA - Applicants: EM Microelectronic-Marin SA - Inventors: Alessandro Venca - Web page: https://patentgrep.com/patent/US12224664B2 ## CPC - H02M 3/07: using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} - H02M 1/08: Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters - H02M 1/36: Means for starting or stopping converters - H02M 3/285: {Single converters with a plurality of output stages connected in parallel (parallel operation of a plurality of converters in DC distribution networks H02J1/10)} - H03K 17/145: {in field-effect transistor switches} - G11C 5/145: {Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence)} - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Provided is a gate controller having a primary signal input which is AC coupled to the gate through a capacitor, one or more bias inputs each connected to the gate through a resistor such as to control the DC voltage bias of the gate and therefore the conductivity o the switching element. The bias inputs can be properly connected to internal nodes of the charge pump, or charge pump stages, such that the gate controller is self-biased, without using bias-reference external to the charge pump. The gate controller is programmable by using potentiometers in place of the bias resistors. The programmable gate controller stages can be connected to form a programmable gate controlled charge pump. ## Claims ### Claim 1 Gate controller (100) for a charge pump converter stage (101), said charge pump converter stage (101) comprising at least one switching element (110) having a conduction path (115) with a first terminal (111) and a second terminal (112), and a gate (113) configured to control the current flowing through said conduction path (115), said conduction path (115) being configured to provide at least one signal; said gate controller (100) comprising at least: one primary signal input (120): said at least one primary signal input (120) is directly connected to a second terminal of another charge pump converter stage to receive a signal from said another charge pump converter stage and to transfer said signal to said first terminal (111) of conduction path (115) of said at least one switching element (110); at least one bias input (130): said at least one bias input (130) is connected to said gate (113) through a resistor (131) and configured to establish a voltage value and/or a current value of said gate (113); and at least one coupling capacitor (140) configured to connect said gate (113) to said at least one primary signal input (120) and to connect said conduction path (115) of said at least one switching element (110) to said gate (113). ### Claim 2 (depends on 1) The gate controller (100) according to claim 1, which comprises at least one primary coupling capacitor (142) configured to be connected directly to said gate (113) and at least one first secondary signal input (151) configured to be connected directly to said at least primary coupling capacitor (142); said at least one first secondary signal input (151) is configured to receive a first control signal. ### Claim 3 (depends on 1) The gate controller (100) according to claim 1, which comprises at least one attenuator (145) and at least one second secondary signal input (152) configured to be connected directly to said at least one attenuator (145); said at least one second secondary signal input (152) is configured to receive at least one secondary signal. ### Claim 4 (depends on 3) The gate controller (100) according to claim 3, wherein said at least one attenuator (145) comprises at least one first secondary capacitor (143) configured to be connected directly between said at least one second secondary signal input (152) and said second terminal (112). ### Claim 5 (depends on 4) The gate controller (100) according to claim 4, wherein said at least one attenuator (145) comprises at least one second secondary capacitor (144) configured to be connected directly between said ground and said second terminal (112). ### Claim 6 (depends on 5) The gate controller (100) according to claim 5, wherein said at least one attenuator (145) comprises at least one first secondary trim input (147) configured to trim the capacitance of said at least one first secondary capacitor (143) and/or the capacitance of said at least one second secondary capacitor (144), and/or wherein said at least one attenuator (145) comprises at least one second secondary trim input (148) configured to trim said capacitance of said at least one second secondary capacitor (144). ### Claim 7 (depends on 1) The gate controller (100) according to claim 1, wherein said at least one bias input (130) is directly connected to said at least one primary signal input (120). ### Claim 8 (depends on 1) The gate controller (100) according to claim 1, wherein said at least one bias input (130) comprises a plurality of bias current flow controller (135) comprising at least one first bias current flow controller (131) and/or at least one first bias transistor (136). ### Claim 9 (depends on 8) The gate controller (100) according to claim 8, wherein said plurality of bias current flow controller (135) comprises at least one second bias current flow controller (132) and/or at least one second bias transistor (137). ### Claim 10 (depends on 9) The gate controller (100) according to claim 9, wherein said at least one second bias current flow controller (132) is directly connected to said gate (113) and said second terminal (112) of conduction path (115) of said at least one switching element (110). ### Claim 11 (depends on 10) The gate controller (100) according to claim 10, wherein said at least one first bias current flow controller (131) comprises at least one resistor, a potentiometer and/or a digital potentiometer, and/or wherein said at least one second bias current flow controller (132) comprises at least one resistor, a potentiometer and/or a digital potentiometer. ### Claim 12 (depends on 10) The gate controller (100) according to claim 10, wherein said at least one first bias current flow controller (131) and/or said at least one first bias transistor (136) comprises or comprise at least one first primary trim input (134) configured to trim the current flowing through said at least one first bias current flow controller (131) and/or said at least one first bias transistor (136), and/or wherein said at least one second bias current flow controller (132) and/or said at least one second bias transistor (137) comprises or comprise at least one second primary trim input (139) configured to trim the current flowing through said at least one first bias current flow controller (131) and/or said at least one first bias transistor (136). ### Claim 13 (depends on 1) The gate controller (100) according to claim 1, wherein said at least one bias input (130) is directly connected to said gate (113) through the resistor (131) and configured to establish a voltage value and/or a current value of said gate (113).