# US 12,224,482 B2 · Antenna effect protection and electrostatic discharge protection for three-dimensional integrated circuit

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,224,482 B2
- Document ID: US12224482B2
- Status: Granted
- Kind: B2
- Application number: 18/448,045
- Filed: 2023-08-10
- Published: 2024-04-11
- Granted: 2025-02-11
- Earliest claimed: 2020-03-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Po-Hsiang Huang; Fong-Yuan Chang; Tsui-Ping Wang; Yi-Shin Chu
- Web page: https://patentgrep.com/patent/US12224482B2

## CPC

- H01Q 1/2283: {mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H01Q 1/50: Structural association of antennas with earthing switches, lead-in devices or lightning protectors
- H01Q 23/00: Antennas with active circuits or circuit elements integrated within them or attached to them
- H10D 89/601: {for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs}
- H10W 20/212: {Top-view shapes or dispositions, e.g. top-view layouts of the vias}
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 90/00: Package configurations
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H01Q: ANTENNAS, i.e. RADIO AERIALS (radiators or antennas for microwave heating H05B6/72)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A 3D IC package is provided. The 3D IC package includes: a first IC die comprising a first substrate at a back side of the first IC die; a second IC die stacked at the back side of the first IC die and facing the first substrate; a TSV through the first substrate and electrically connecting the first IC die and the second IC die, the TSV having a TSV cell including a TSV cell boundary surrounding the TSV; and a protection module fabricated in the first substrate, wherein the protection module is electrically connected to the TSV, and the protection module is within the TSV cell.

## Claims

### Claim 1

A three-dimensional (3D) integrated circuit (IC) package, comprising:
a first IC die comprising a first substrate at a back side of the first IC die;
a second IC die stacked at the back side of the first IC die and facing the first substrate;
a through-substrate via (TSV) through the first substrate and electrically connecting the first IC die and the second IC die, the TSV comprising a TSV cell having a TSV cell boundary surrounding the TSV; and
at least one diode fabricated in the first substrate, wherein the at least one diode is electrically connected to the TSV, wherein the at least one diode is fabricated within the TSV cell boundary surrounding the TSV, and wherein no functional cell is fabricated within the TSV cell boundary.

### Claim 2 (depends on 1)

The 3D IC package of claim 1, wherein the at least one diode is configured to provide antenna effect protection to the first IC die.

### Claim 3 (depends on 1)

The 3D IC package of claim 1, further comprises multiple diodes connected in parallel.

### Claim 4 (depends on 1)

The 3D IC package of claim 1, wherein the at least one diode is one of: a bipolar transistor, a metal-oxide-semiconductor field-effect transistor (MOSFET), and a silicon-controlled rectifier (SCR).

### Claim 5 (depends on 1)

The 3D IC package of claim 1, wherein the TSV cell is a keep-out zone (KOZ) of the TSV.

### Claim 6 (depends on 1)

The 3D IC package of claim 1, wherein the protection module is outside a TSV buffer zone of the TSV.

### Claim 7 (depends on 1)

The 3D IC package of claim 1, wherein the TSV cell has a plurality of rows, and the protection module is placed on one of the plurality of rows.

### Claim 8 (depends on 1)

The 3D IC package of claim 1, wherein the first IC die comprises a transistor in a functional cell, the transistor having an enlarged gate polysilicon area.

### Claim 9

A three-dimensional (3D) integrated circuit (IC) package, comprising:
a first IC die comprising a first substrate at a back side of the first IC die;
a second IC die stacked at the back side of the first IC die and facing the first substrate;
a hybrid bonding (HB) structure bonding the first IC die and the second IC die, the HB structure having a HB region surrounding the HB structure; and
a transistor fabricated in the first substrate, wherein the transistor is electrically connected to the HB structure, the transistor is fabricated within the HB region surrounding the HB structure, and wherein no functional cell is fabricated within the HB region.

### Claim 10 (depends on 9)

The 3D IC package of claim 9, wherein the transistor is configured to provide antenna effect protection to the first IC die.

### Claim 11 (depends on 9)

The 3D IC package of claim 9, wherein the transistor comprises multiple diodes connected in parallel.

### Claim 12 (depends on 9)

The 3D IC package of claim 9, wherein the protection module is electrically connected to the HB structure through a multi-layer interconnect (MLI) structure.

### Claim 13 (depends on 12)

The 3D IC package of claim 12, wherein the HB structure comprises a HB metal layer and a HB contact structure, the HB contact structure electrically connecting the HB metal layer and the MLI structure.

### Claim 14 (depends on 9)

The 3D IC package of claim 9, wherein the transistor is one of: a bipolar transistor, a metal-oxide-semiconductor field-effect transistor (MOSFET), and a silicon-controlled rectifier (SCR).

### Claim 15

A method, comprising:
providing a first IC die comprising a first substrate at a back side of the first IC die;
fabricating a through-substrate via (TSV) through the first substrate, the TSV comprising a TSV cell having a TSV cell boundary surrounding the TSV;
fabricating an electrostatic discharge (ESD)_protection module in the first substrate, wherein the ESD protection module is electrically connected to the TSV, wherein the ESD protection module is within the TSV cell boundary surrounding the TSV, and wherein no functional cell is fabricated within the TSV cell boundary;
providing a second IC die at a front side of the first IC die; and
bonding the second IC die to the first IC die, the first IC die and the second IC die being electrically connected through the TSV.

### Claim 16 (depends on 15)

The method of claim 15, wherein the ESD protection module is an antenna protection module configured to provide antenna effect protection to the first IC die.

### Claim 17 (depends on 15)

The method of claim 15, wherein the ESD protection module comprises one of the following: a diode, a bipolar transistor, a metal-oxide-semiconductor field-effect transistor (MOSFET), and a silicon-controlled rectifier (SCR).

### Claim 18 (depends on 15)

The method of claim 15, wherein the ESD protection module comprises a plurality of diodes connected in parallel.

### Claim 19 (depends on 15)

The method of claim 15, wherein the ESD protection module is outside a TSV buffer zone of the TSV.

### Claim 20 (depends on 15)

The method package of claim 15, wherein the TSV cell has a plurality of rows, and the ESD protection module is placed on one of the plurality of rows.