# US 12,224,357 B2 · Semiconductor transistor device including multiple channel layers with different materials

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,224,357 B2
- Document ID: US12224357B2
- Status: Granted
- Kind: B2
- Application number: 17/804,102
- Filed: 2022-05-26
- Published: 2023-01-12
- Granted: 2025-02-11
- Earliest claimed: 2021-07-12
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jinyeong Joe; Dongchan Suh; Sungkeun Lim; Seokhoon Kim; Pankwi Park; Dongsuk Shin
- Web page: https://patentgrep.com/patent/US12224357B2

## CPC

- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/0194: {the stacked channels having different properties}
- H10D 30/0195: {forming inner spacers between adjacent channels, e.g. changing their shapes or sizes}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/506: {having different thicknesses, sizes or shapes}
- H10D 30/508: {characterised by the relative sizes, shapes or dispositions of the inner spacers}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/364: {of IGFETs}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device includes a first active region, a second active region spaced apart from the first active region, a plurality of first channel layers disposed on the first active region, and a second channel layer disposed on the second active region. The semiconductor device further includes a first gate structure intersecting the first active region and the first channel layers, a second gate structure intersecting the second active region and the second channel layer, a first source/drain region disposed on the first active region and contacting the plurality of first channel layers, and a second source/drain region and contacting the second channel layer. The plurality of first channel layers includes a first uppermost channel layer and first lower channel layers disposed below the first uppermost channel layer, and the first uppermost channel layer includes a material that is different from a material included in the first lower channel layers.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate;
active regions disposed on the substrate, the active regions including:
a first active region extending on the substrate in a horizontal direction parallel to an upper surface of the substrate, and
a second active region spaced apart from the first active region;
a plurality of channel layers disposed on the active regions, the plurality of channel layers including:
a plurality of first channel layers disposed on the first active region, wherein first channel layers of the plurality of first channel layers are spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate, and
a second channel layer disposed on the second active region;
gate structures disposed on the substrate, the gate structures including:
a first gate structure intersecting the first active region and the first channel layers, and
a second gate structure intersecting the second active region and the second channel layer; and
source/drain regions disposed on the active regions, the source/drain regions including:
a first source/drain region disposed on the first active region on at least one side of the first gate structure and contacting the plurality of first channel layers, and
a second source/drain region disposed on the second active region on at least one side of the second gate structure and contacting the second channel layer,
wherein the plurality of first channel layers includes a first uppermost channel layer and first lower channel layers disposed below the first uppermost channel layer, and the first uppermost channel layer includes a material that is different from a material included in the first lower channel layers.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first lower channel layers and the second channel layer include silicon (Si), and the first uppermost channel layer includes silicon carbide.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein a composition of carbon (C) in the first uppermost channel layer ranges from about 0.5% to about 3% by weight or by mass.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the second channel layer has a thickness greater than a sum of thicknesses of the first channel layers.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein an uppermost surface of the first uppermost channel layer and an uppermost surface of the second channel layer are disposed at a substantially similar height.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein:
the first uppermost channel layer includes:
a first central region vertically overlapping the first gate structure, and
first peripheral regions disposed on opposing sides of the first central region; and
a first thickness of the first uppermost channel layer in the first central region is greater than a second thickness of the first uppermost channel layer in the first peripheral regions.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the first thickness ranges from about 70 Å to about 120 Å, and the second thickness ranges from about 50 Å to about 100 Å.

### Claim 8 (depends on 6)

The semiconductor device of claim 6, further comprising first spacer structures disposed on opposing sidewalls of the first gate structure, wherein the first peripheral regions vertically overlap the first spacer structures.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein an upper surface of the first central region contacts the first gate structure, and upper surfaces of the first peripheral regions contact the first spacer structures.

### Claim 10 (depends on 6)

The semiconductor device of claim 6, wherein:
the second channel layer includes:
a second central region vertically overlapping the second gate structure, and
second peripheral regions disposed on opposing sides of the second central region; and
a third thickness of the second channel layer in the first central region is greater than a fourth thickness of the second channel layer in the second peripheral regions.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein a difference between the first thickness and the second thickness is smaller than a difference between the third thickness and the fourth thickness.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, wherein:
the first gate structure includes an inclined sidewall inclined at an obtuse angle from a bottom portion of the first gate structure, and a width of the inclined sidewall at a lower end of the inclined sidewall is less than a width of the inclined sidewall at an upper end of the inclined sidewall;
the first uppermost channel layer includes:
a first central region contacting the first gate structure, and
first peripheral regions disposed on opposing sides of the first central region; and
a first thickness in the first central region is greater than a second thickness in the second peripheral regions.

### Claim 13 (depends on 1)

The semiconductor device of claim 1, wherein:
the first uppermost channel layer includes:
a first central region vertically overlapping the first gate structure, and
first peripheral regions disposed on both sides of the first central region;
a first thickness of the first uppermost channel layer in the first central region and a second thickness of the first uppermost channel layer in the first peripheral regions are substantially equal; and
the first thickness is greater than a thickness of each of the first lower channel layers.

### Claim 14 (depends on 1)

The semiconductor device of claim 1, wherein the first lower channel layers include silicon (Si), and the first uppermost channel layer and the second channel layer include silicon carbide.

### Claim 15

A semiconductor device comprising:
a substrate;
a first transistor disposed on the substrate, the first transistor including:
a first active region extending on the substrate in a first horizontal direction parallel to an upper surface of the substrate,
a plurality of first channel layers disposed on the first active region, wherein first channel layers of the plurality of first channel layers are spaced apart from each other, the first channel layers including a first uppermost channel layer and first lower channel layers,
a first gate structure intersecting the first active region and the plurality of first channel layers, and extending in a second horizontal direction, and
a first source/drain region disposed on the first active region on at least one side of the first gate structure and contacting the plurality of first channel layers; and
a second transistor disposed on the substrate, the second transistor including:
a second active region spaced apart from the first active region,
a second channel layer disposed on the second active region,
a second gate structure intersecting the second active region and the second channel layer, and extending in a vertical direction perpendicular to the upper surface of the substrate, and
a second source/drain region disposed on the second active region on at least one side of the second gate structure and contacting the second channel layer,
wherein a threshold voltage of the first transistor is lower than a threshold voltage of the second transistor,
wherein the first uppermost channel layer is thicker than each of the first lower channel layers,
wherein the second channel layer has a thickness greater than a sum of thicknesses of the first channel layers of the plurality of first channel layers, and
wherein the second channel layer includes a material that is different from a material included in the first uppermost channel layer.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the first lower channel layers and the second channel layer include silicon (Si), and the first uppermost channel layer includes silicon carbide.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein the plurality of first channel layers include silicon (Si), and the second channel layer includes silicon carbide.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, wherein the first uppermost channel layer includes:
a silicon layer having a thickness substantially equal to a thickness of each of the first lower channel layers, and
a silicon carbide layer disposed on the silicon layer.

### Claim 19

A semiconductor device comprising:
a substrate;
an active region disposed on the substrate and extending on the substrate in a first horizontal direction parallel to an upper surface of the substrate;
a plurality of channel layers disposed on the active region, the plurality of channel layers including:
at least one lower channel layer disposed on the active region, the at least one lower channel layer including silicon, and
an uppermost channel layer disposed on the at least one lower channel layer and spaced apart from the at least one lower channel layer in a vertical direction perpendicular to the upper surface of the substrate, wherein the uppermost channel layer has a thickness greater than a thickness of the at least one lower channel layer, includes a material that is different from a material included in the at least one lower channel layer, and includes silicon carbide;
a gate structure disposed on the substrate, intersecting the active region and the plurality of channel layers, and extending in a second horizontal direction, wherein the gate structure includes a gate electrode surrounding the plurality of channel layers;
spacer structures disposed on opposing sidewalls of the gate structure; and
a source/drain region disposed on the active region on at least one side of the gate structure and contacting the plurality of channel layers.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein:
the uppermost channel layer includes:
a central region vertically overlapping the gate structure, and
peripheral regions disposed on opposing sides of the central region; and
a first thickness of the uppermost channel layer in the central region is greater than a second thickness of the uppermost channel layer in the peripheral regions.