# US 12,224,355 B2 · Semiconductor device and manufacturing method thereof

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- Number: US 12,224,355 B2
- Document ID: US12224355B2
- Status: Granted
- Kind: B2
- Application number: 18/504,297
- Filed: 2023-11-08
- Published: 2024-02-29
- Granted: 2025-02-11
- Earliest claimed: 2008-12-26
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Shunpei Yamazaki; Junichiro Sakata; Jun Koyama
- Web page: https://patentgrep.com/patent/US12224355B2

## CPC

- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/80: characterised by the materials
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10P 14/22: using physical deposition, e.g. vacuum deposition or sputtering
- H10P 14/3426: {Oxides}
- H10P 14/3434: {being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device which includes a thin film transistor having an oxide semiconductor layer and excellent electrical characteristics is provided. Further, a method for manufacturing a semiconductor device in which plural kinds of thin film transistors of different structures are formed over one substrate to form plural kinds of circuits and in which the number of steps is not greatly increased is provided. After a metal thin film is formed over an insulating surface, an oxide semiconductor layer is formed thereover. Then, oxidation treatment such as heat treatment is performed to oxidize the metal thin film partly or entirely. Further, structures of thin film transistors are different between a circuit in which emphasis is placed on the speed of operation, such as a logic circuit, and a matrix circuit.

## Claims

### Claim 1

A semiconductor device comprising a transistor comprising:
a first conductive layer;
a first metal oxide layer having a region provided over the first conductive layer;
a second metal oxide layer having a region provided over the first metal oxide layer;
a third metal oxide layer having a region provided over a first region of the second metal oxide layer;
a fourth metal oxide layer having a region provided over a second region of the second metal oxide layer; and
a second conductive layer having a region provided over the third metal oxide layer, the second conductive layer electrically connected to the third metal oxide layer,
wherein the second metal oxide layer comprises a depression part between the first region and the second region,
wherein the depression part of the second metal oxide layer is in contact with an insulating layer provided over the second metal oxide layer,
wherein a conductivity of the first metal oxide layer is higher than a conductivity of the second metal oxide layer,
wherein each of a conductivity of the third metal oxide layer and a conductivity of the fourth metal oxide layer is higher than the conductivity of the second metal oxide layer, and
wherein an end portion of the second metal oxide layer has a shape with a lower part protruding from an upper part.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the first conductive layer is configured to be a gate electrode of the transistor.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the second metal oxide layer is thicker than the first metal oxide layer.

### Claim 4

A semiconductor device comprising a transistor comprising:
a first conductive layer;
a first metal oxide layer having a region provided over the first conductive layer;
a second metal oxide layer having a region provided over the first metal oxide layer;
a third metal oxide layer having a region provided over a first region of the second metal oxide layer;
a fourth metal oxide layer having a region provided over a second region of the second metal oxide layer; and
a second conductive layer having a region provided over the third metal oxide layer, the second conductive layer electrically connected to the third metal oxide layer,
wherein the first metal oxide layer comprises indium and zinc,
wherein the second metal oxide layer comprises indium, zinc, and gallium,
wherein the second metal oxide layer comprises a depression part between the first region and the second region,
wherein the depression part of the second metal oxide layer is in contact with an insulating layer provided over the second metal oxide layer,
wherein a conductivity of the first metal oxide layer is higher than a conductivity of the second metal oxide layer,
wherein each of a conductivity of the third metal oxide layer and a conductivity of the fourth metal oxide layer is higher than the conductivity of the second metal oxide layer, and
wherein an end portion of the second metal oxide layer has a shape with a lower part protruding from an upper part.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4, wherein the first conductive layer is configured to be a gate electrode of the transistor.

### Claim 6 (depends on 4)

The semiconductor device according to claim 4, wherein the second metal oxide layer is thicker than the first metal oxide layer.

### Claim 7 (depends on 4)

The semiconductor device according to claim 4, wherein each of the third metal oxide layer and the fourth metal oxide layer comprises indium, zinc, and gallium.

### Claim 8

A semiconductor device comprising a transistor comprising:
a first conductive layer;
a first metal oxide layer having a region provided over the first conductive layer;
a second metal oxide layer having a region provided over the first metal oxide layer;
a third metal oxide layer having a region provided over a first region of the second metal oxide layer;
a fourth metal oxide layer having a region provided over a second region of the second metal oxide layer; and
a second conductive layer having a region provided over the third metal oxide layer, the second conductive layer electrically connected to the third metal oxide layer,
wherein the second metal oxide layer comprises a depression part between the first region and the second region,
wherein the depression part of the second metal oxide layer is in contact with an insulating layer provided over the second metal oxide layer,
wherein a conductivity of the first metal oxide layer is higher than a conductivity of the second metal oxide layer,
wherein each of a conductivity of the third metal oxide layer and a conductivity of the fourth metal oxide layer is higher than the conductivity of the second metal oxide layer, and
wherein an end portion of the second metal oxide layer has a shape with a lower part extending beyond an upper part.

### Claim 9 (depends on 8)

The semiconductor device according to claim 8, wherein the first conductive layer is configured to be a gate electrode of the transistor.

### Claim 10 (depends on 8)

The semiconductor device according to claim 8, wherein the second metal oxide layer is thicker than the first metal oxide layer.

### Claim 11 (depends on 8)

The semiconductor device according to claim 8,
wherein the first metal oxide layer comprises indium and zinc, and
wherein the second metal oxide layer comprises indium, zinc, and gallium.

### Claim 12 (depends on 11)

The semiconductor device according to claim 11, wherein each of the third metal oxide layer and the fourth metal oxide layer comprises indium, zinc, and gallium.
