# US 12,224,354 B2 · Oxide thin film transistor, display panel and preparation method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,224,354 B2 - Document ID: US12224354B2 - Status: Granted - Kind: B2 - Application number: 17/597,027 - Filed: 2021-12-06 - Published: 2023-05-18 - Granted: 2025-02-11 - Earliest claimed: 2021-11-18 - Assignees: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. - Applicants: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. - Inventors: Ding Ding; Liang Fang - Web page: https://patentgrep.com/patent/US12224354B2 ## CPC - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10D 30/6715: {characterised by the doping profiles, e.g. having lightly-doped source or drain extensions} - H10D 30/6733: {Multi-gate TFTs} - H10D 30/6739: {Conductor-insulator-semiconductor electrodes} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies} - H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO} - H10D 86/60: wherein the TFTs are in active matrices - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract The present application discloses an oxide thin film transistor, a display panel, and a preparation method thereof. Each thickness of the first gate insulating layer of the present application corresponding to the first source doped region, the first drain doped region, the first diffusion region, and the second diffusion region is less than a thickness corresponding to the first channel region; and thicknesses of the first gate insulating layer corresponding to the first diffusion region and the second diffusion region are both different from a thickness corresponding to the first source doped region and the first drain doped region. The the first gate insulating layer effectively shields the first channel region laterally. ## Claims ### Claim 1 An oxide thin film transistor, comprising a substrate, a first active layer on the substrate, a second gate between the substrate and the first active layer, a first gate insulating layer disposed on one side of the first active layer away from the substrate, a first gate disposed on one side of the first gate insulating layer away from the substrate, a first interlayer insulating layer disposed on one side of the first gate away from the substrate, and a source/drain layer disposed on one side of the first interlayer insulating layer away from the substrate, wherein the source/drain layer comprises a first source and a first drain; the first active layer comprises a first source doped region, a first channel region, a first drain doped region, a first diffusion region between the first source doped region and the first channel region, and a second diffusion region between the first drain doped region and the first channel region; wherein the first source is electrically connected to the first source doped region, and the first drain is electrically connected to the first drain doped region; each thickness of the first gate insulating layer corresponding to the first source doped region, the first drain doped region, the first diffusion region, and the second diffusion region is less than a thickness corresponding to the first channel region; and thicknesses of the first gate insulating layer corresponding to the first diffusion region and the second diffusion region are both different from a thickness corresponding to the first source doped region and the first drain doped region. ### Claim 2 (depends on 1) The oxide thin film transistor according to claim 1, wherein both of thicknesses of the first gate insulating layer corresponding to the first diffusion region and the second diffusion region are greater than a thickness corresponding to the first source doped region and the first drain doped region. ### Claim 3 (depends on 1) The oxide thin film transistor according to claim 1, wherein the first gate insulating layer is provided with a first step corresponding to the first source doped region and the first drain doped region, the first gate insulating layer is provided with a second step corresponding to the first diffusion region and the second diffusion region, and one side of the second step close to the first channel region is flush with one side of the first gate. ### Claim 4 (depends on 3) The oxide thin film transistor according to claim 3, wherein a height of the second step is greater than a height of the first step. ### Claim 5 (depends on 1) The oxide thin film transistor according to claim 1, wherein the first active layer is doped with a conductive particle; both of doping concentrations of the conductive particle in the first source doped region and the first drain doped region are greater than doping concentrations of the conductive particle in the first diffusion region and the second diffusion region; and both of doping concentrations of the conductive particle in the first diffusion region and the second diffusion region are greater than doping concentration of the conductive particle in the first channel region. ### Claim 6 (depends on 5) The oxide thin film transistor according to claim 5, wherein both of the first source doped region and the first drain doped region are doped with boron ions, wherein a concentration of the boron ions ranges from 1×1012 ions/cm2 to 1×1014 ions/cm2. ### Claim 7 (depends on 5) The oxide thin film transistor according to claim 5, wherein the conductive particle comprises one of boron ions, nitrogen ions or phosphorus ions. ### Claim 8 A display panel, comprising: a substrate; a driving circuit layer disposed on one side of a substrate, and the driving circuit layer comprises a first active layer, a first gate insulating layer disposed on one side of the first active layer away from the substrate, a first gate disposed on one side of the first gate insulating layer away from the substrate, a second gate between the substrate and the first active layer, a first interlayer insulating layer disposed on one side of the first gate away from the substrate, and a source/drain layer disposed on one side of the first interlayer insulating layer away from the substrate, wherein the source/drain layer comprises a first source and a first drain; wherein the first active layer comprises a first source doped region, a first channel region, a first drain doped region, a first diffusion region between the first source doped region and the first channel region, and a second diffusion region between the first drain doped region and the first channel region; wherein the first source is electrically connected to the first source doped region, and the first drain is electrically connected to the first drain doped region; each thickness of the first gate insulating layer corresponding to the first source doped region, the first drain doped region, the first diffusion region, and the second diffusion region is less than a thickness corresponding to the first channel region; and thicknesses of the first gate insulating layer corresponding to the first diffusion region and the second diffusion region are both different from a thickness corresponding to the first source doped region and the first drain doped region. ### Claim 9 (depends on 8) The display panel according to claim 8, wherein both of thicknesses of the first gate insulating layer corresponding to the first diffusion region and the second diffusion region are greater than thicknesses of the first source doped region and the first drain doped region corresponding to the first gate insulating layer. ### Claim 10 (depends on 8) The display panel according to claim 8, wherein the first gate insulating layer is provided with a first step corresponding to the first source doped region and the first drain doped region, the first gate insulating layer is provided with a second step corresponding to the first diffusion region and the second diffusion region, and one side of the second step close to the first channel region is flush with one side of the first gate. ### Claim 11 (depends on 8) The display panel according to claim 8, wherein the first active layer is doped with a conductive particle; both of doping concentrations of the conductive particle in the first source doped region and the first drain doped region are greater than that doping concentrations of the conductive particle in the first diffusion region and the second diffusion region; and both of doping concentrations of the conductive particle in the first diffusion region and the second diffusion region are greater than doping concentration of the conductive particle in the first channel region. ### Claim 12 (depends on 11) The display panel according to claim 11, wherein the conductive particle comprises one of boron ions, nitrogen ions, or phosphorus ions. ### Claim 13 (depends on 8) The display panel according to claim 8, wherein the drive circuit layer further comprises at least a second active layer, a third gate, a fourth gate, a second source and a second drain disposed above the substrate, the second gate and the fourth gate are disposed in a same layer, and the first source, the first drain, the second source and the second drain are disposed in a same layer. ### Claim 14 (depends on 13) The display panel according to claim 13, wherein the first active layer is a metal oxide semiconductor layer, and the second active layer is a low-temperature polysilicon semiconductor layer. ### Claim 15 (depends on 13) The display panel according to claim 13, wherein the driving circuit layer further comprises a light shielding electrode layer, the light shielding electrode layer covers the first active layer, and the light shielding electrode layer is electrically connected to the second source. ### Claim 16 (depends on 15) The display panel according to claim 15, wherein the light shielding electrode layer comprises one of molybdenum, copper, chromium, tungsten, tantalum, or titanium. ### Claim 17 A method for preparing a display panel, the display panel comprises a substrate and a drive circuit layer on one side of the substrate, wherein the method comprises: step S1: providing a substrate, and forming at least a first active layer, a first gate insulating layer, a first gate layer, and a photoresist layer on the substrate; wherein the first active layer comprises a first source doped region, a first channel region, a first drain doped region, a first diffusion region between the first source doped region and the first channel region, and a second diffusion region between the first drain doped region and the first channel region; step S2: patterning the photoresist layer to form a first photoresist pattern that does not block the first source doped region and the first drain doped region of the first active layer; step S3: etching the first gate layer and the first gate insulating layer by using the first photoresist pattern as a barrier layer, so that both thicknesses of the first gate insulating layer corresponding to the first source doped region and the first drain doped region are smaller than a thickness corresponding to the first diffusion region, the second diffusion region, and the first channel region; and simultaneously doping a conductive particle from the first gate insulating layer to the first source doped region and the first drain doped region; step S4: patterning the first photoresist pattern to form a second photoresist pattern, etching the first gate layer and the first gate insulating layer by using the first photoresist pattern as a barrier layer again, so that each thickness of the first gate insulating layer corresponding to the first diffusion region and the second diffusion region is less than a thicknesses corresponding to the first channel region; and stripping the second photoresist pattern; and step S5: forming an interlayer insulating layer on the first gate insulating layer, and forming a first source and a first drain on the interlayer insulating layer, wherein the first source and the first drain are electrically connected to the first source doped region and the first drain doped region through a source contact hole and a drain contact hole, respectively. ### Claim 18 (depends on 17) The method according to claim 17, wherein the conductive particle in the step S3 comprises one of boron ions, nitrogen ions, or phosphorus ions. ### Claim 19 (depends on 18) The method according to claim 18, wherein both of doping concentrations of the conductive particle in the first source doped region and the first drain doped region are greater than that doping concentrations of the conductive particle in the first diffusion region and the second diffusion region; and both of doping concentrations of the conductive particle in the first diffusion region and the second diffusion region are greater than doping concentration of the conductive particle in the first channel region.