# US 12,224,350 B2 · Self-aligned gate endcap (SAGE) architectures with gate-all-around devices

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- Number: US 12,224,350 B2
- Document ID: US12224350B2
- Status: Granted
- Kind: B2
- Application number: 18/374,959
- Filed: 2023-09-29
- Published: 2024-01-25
- Granted: 2025-02-11
- Earliest claimed: 2018-06-25
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Biswajeet Guha; William Hsu; Leonard P. Guler; Dax M. Crum; Tahir Ghani
- Web page: https://patentgrep.com/patent/US12224350B2

## CPC

- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6217: {having non-uniform gate electrodes, e.g. gate conductors having varying doping}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/119: {Nanowire, nanosheet or nanotube semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/364: {of IGFETs}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10P 14/3462: {Nanowires}
- H10W 20/42: Vias, e.g. via plugs
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 84/0128: {Manufacturing their channels}
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.

## Claims

### Claim 1

An integrated circuit structure, comprising:
a first fin extending above a trench isolation structure;
a second fin extending above the trench isolation structure, the second fin laterally spaced apart from the first fin; and
a gate endcap isolation structure between the first fin and the second fin, the gate endcap isolation structure over and extending into the trench isolation structure, the gate endcap isolation structure laterally spaced apart and separated from the first fin, and the gate endcap isolation structure laterally spaced apart and separated from the second fin.

### Claim 2 (depends on 1)

The integrated circuit structure of claim 1, wherein the gate endcap isolation structure extends only partially into the trench isolation structure.

### Claim 3 (depends on 1)

The integrated circuit structure of claim 1, further including:
a first nanowire vertically over the first fin; and
a second nanowire vertically over the second fin.

### Claim 4 (depends on 1)

The integrated circuit structure of claim 1, wherein the first fin is wider than the second fin.

### Claim 5 (depends on 1)

The integrated circuit structure of claim 1, further including:
a first gate stack over the first fin; and
a second gate stack over the second fin.

### Claim 6 (depends on 5)

The integrated circuit structure of claim 5, wherein the gate endcap isolation structure laterally separates the first gate stack from the second gate stack, and wherein the gate endcap isolation structure is in contact with the first gate stack and the second gate stack.

### Claim 7 (depends on 5)

The integrated circuit structure of claim 5, wherein each of the first gate stack and the second gate stack includes a gate dielectric and a gate electrode, the integrated circuit structure further including:
a first pair of source or drain structures on either side of the first gate stack; and
a second pair of source or drain structures on either side of the second gate stack.

### Claim 8 (depends on 1)

The integrated circuit structure of claim 1, wherein the gate endcap isolation structure includes a lower dielectric portion and a dielectric cap on the lower dielectric portion.

### Claim 9

An integrated circuit structure, comprising:
a first isolation structure having an uppermost surface;
a first fin having a bottom below the uppermost surface of the first isolation structure, the first fin having a top above the uppermost surface of the first isolation structure;
a second fin having a bottom below the uppermost surface of the first isolation structure, the second fin having a top above the uppermost surface of the first isolation structure, the second fin laterally spaced apart from the first fin; and
a second isolation structure between the first fin and the second fin, the second isolation structure vertically over the first isolation structure, the second isolation structure having a bottom below the uppermost surface of the first isolation structure and having a top above the first fin and the second fin, the second isolation structure laterally spaced apart and separated from the first fin, and the second isolation structure laterally spaced apart and separated from the second fin.

### Claim 10 (depends on 9)

The integrated circuit structure of claim 9, wherein the second isolation structure extends only partially into the first isolation structure.

### Claim 11 (depends on 9)

The integrated circuit structure of claim 9, further including:
a first nanowire vertically over the first fin; and
a second nanowire vertically over the second fin.

### Claim 12 (depends on 9)

The integrated circuit structure of claim 9, wherein the first fin is wider than the second fin.

### Claim 13 (depends on 9)

The integrated circuit structure of claim 9, further including:
a first gate stack over the first fin; and
a second gate stack over the second fin.

### Claim 14 (depends on 13)

The integrated circuit structure of claim 13, wherein the second isolation structure laterally separates the first gate stack from the second gate stack, and wherein the second isolation structure is in contact with the first gate stack and the second gate stack.

### Claim 15 (depends on 13)

The integrated circuit structure of claim 13, wherein each of the first gate stack and the second gate stack includes a gate dielectric and a gate electrode, the integrated circuit structure further including:
a first pair of source or drain structures on either side of the first gate stack; and
a second pair of source or drain structures on either side of the second gate stack.

### Claim 16 (depends on 9)

The integrated circuit structure of claim 9, wherein the second isolation structure includes a lower dielectric portion and a dielectric cap on the lower dielectric portion.

### Claim 17

A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, including:
a first fin extending above a trench isolation structure;
a second fin extending above the trench isolation structure, the second fin laterally spaced apart from the first fin; and
a gate endcap isolation structure between the first fin and the second fin, the gate endcap isolation structure over and extending into the trench isolation structure, the gate endcap isolation structure laterally spaced apart and separated from the first fin, and the gate endcap isolation structure laterally spaced apart and separated from the second fin.

### Claim 18 (depends on 17)

The computing device of claim 17, further including a memory coupled to the board.

### Claim 19 (depends on 17)

The computing device of claim 17, further including a communication chip coupled to the board.

### Claim 20 (depends on 17)

The computing device of claim 17, wherein the component is a packaged integrated circuit die.