# US 12,224,348 B2 · Semiconductor device structure and method for forming the same

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- Number: US 12,224,348 B2
- Document ID: US12224348B2
- Status: Granted
- Kind: B2
- Application number: 18/635,530
- Filed: 2024-04-15
- Published: 2024-08-15
- Granted: 2025-02-11
- Earliest claimed: 2019-04-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Kuo-Cheng Chiang; Shi-Ning Ju; Ching-Wei Tsai; Kuan-Lun Cheng; Chih-Hao Wang
- Web page: https://patentgrep.com/patent/US12224348B2

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0153: {using gate cut processes}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/834: {comprising FinFETs}
- H10D 84/853: {comprising FinFETs}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a plurality of nanowire structures over a channel region of a semiconductor fin structure, a source/drain feature on a source/drain region of the semiconductor fin structure, and a dielectric fin structure spaced apart from the source/drain feature and the semiconductor fin structure. A top surface of the dielectric fin structure is higher than a top surface of a bottommost one of the nanowire structures, and a bottom surface of the dielectric fin structure is lower than a bottom surface of the source/drain feature.

## Claims

### Claim 1

A semiconductor device structure, comprising:
a plurality of nanowire structures over a channel region of a semiconductor fin structure;
a source/drain feature on a source/drain region of the semiconductor fin structure; and
a dielectric fin structure spaced apart from the source/drain feature and the semiconductor fin structure, wherein a top surface of the dielectric fin structure is higher than a top surface of a bottommost one of the nanowire structures, and a bottom surface of the dielectric fin structure is lower than a bottom surface of the source/drain feature.

### Claim 2 (depends on 1)

The semiconductor device structure as claimed in claim 1, further comprising:
a source/drain spacer interposed between the source/drain feature and the dielectric fin structure.

### Claim 3 (depends on 1)

The semiconductor device structure as claimed in claim 1, further comprising:
an isolation structure interposed between the semiconductor fin structure and the dielectric fin structure.

### Claim 4 (depends on 3)

The semiconductor device structure as claimed in claim 3, wherein the isolation structure includes a portion under the dielectric fin structure.

### Claim 5 (depends on 1)

The semiconductor device structure as claimed in claim 1, further comprising:
a gate stack wrapping around the plurality of nanowire structures.

### Claim 6 (depends on 5)

The semiconductor device structure as claimed in claim 5, further comprising:
a protection layer on the dielectric fin structure; and
an isolation structure through the gate stack and on the protection layer.

### Claim 7 (depends on 1)

The semiconductor device structure as claimed in claim 1, further comprising:
an interlayer dielectric layer over the source/drain feature; and
an isolation structure through the interlayer dielectric layer and on the dielectric fin structure.

### Claim 8 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the top surface of the dielectric fin structure is lower than a bottom surface of a topmost one of the nanowire structures.

### Claim 9

A semiconductor device structure, comprising:
a semiconductor fin structure and a dielectric fin structure on a substrate;
an isolation structure surrounding the semiconductor fin structure and a portion of the dielectric fin structure;
a source/drain feature on the semiconductor fin structure; and
source/drain spacers on the isolation structure and surrounding a body portion of the source/drain feature, wherein a head portion of the source/drain feature protrudes from between the source/drain spacers, and one of the source/drain spacers is sandwiched between the body portion of the source/drain feature and the dielectric fin structure.

### Claim 10 (depends on 9)

The semiconductor device structure as claimed in claim 9, wherein a ratio of a height of the body portion of the source/drain feature to a height of the head portion of the source/drain feature ranges from about 1.5 to about 6.

### Claim 11 (depends on 9)

The semiconductor device structure as claimed in claim 9, wherein the body portion of the source/drain feature has a substantially consistent width or an upwardly tapering width.

### Claim 12 (depends on 9)

The semiconductor device structure as claimed in claim 9, wherein a dielectric constant of the source/drain spacers is greater than a dielectric constant of the dielectric fin structure.

### Claim 13 (depends on 9)

The semiconductor device structure as claimed in claim 9, further comprising:
a contact etching stop layer along a surface of the head portion of the source/drain feature; and
an interlayer dielectric layer over the contact etching stop layer.

### Claim 14 (depends on 13)

The semiconductor device structure as claimed in claim 13, wherein the contact etching stop layer extends along an upper surface of the dielectric fin structure.

### Claim 15 (depends on 9)

The semiconductor device structure as claimed in claim 9, further comprising:
a plurality of nanostructures over the semiconductor fin structure;
a gate stack wrapping around the plurality of nanostructures; and
a gate spacer along a sidewall of the gate stack, wherein the source/drain spacers extend under the gate spacer.

### Claim 16

A method for forming a semiconductor device structure, comprising:
forming a dummy gate structure across a semiconductor fin structure and a dielectric fin structure;
forming a source/drain spacer on a sidewall of the dummy gate structure to fill a trench between the semiconductor fin structure and the dielectric fin structure;
forming a gate spacer along the sidewall of the dummy gate structure and on the source/drain spacer, the semiconductor fin structure and the dielectric fin structure; and
etching the semiconductor fin structure to form a recess, wherein the source/drain spacer is recessed during etching the semiconductor fin structure.

### Claim 17 (depends on 16)

The method for forming the semiconductor device structure as claimed in claim 16, further comprising:
forming an epitaxial material to overfill the recess.

### Claim 18 (depends on 16)

The method for forming the semiconductor device structure as claimed in claim 16, further comprising:
forming a stack including first semiconductor layers and second semiconductor layers alternatingly stacked over the substrate; and
etching the stack and the substrate to form the semiconductor fin structure.

### Claim 19 (depends on 16)

The method for forming the semiconductor device structure as claimed in claim 16, further comprising:
forming an insulating layer along the semiconductor fin structure;
forming the dielectric fin structure on the insulating layer; and
recessing the insulating layer.

### Claim 20 (depends on 16)

The method for forming the semiconductor device structure as claimed in claim 16, further comprising:
forming a protection layer on the dielectric fin structure, wherein the protection layer is recessed during etching the semiconductor fin structure.