# US 12,224,344 B2 · Method and system for control of sidewall orientation in vertical gallium nitride field effect transistors

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- Number: US 12,224,344 B2
- Document ID: US12224344B2
- Status: Granted
- Kind: B2
- Application number: 17/707,835
- Filed: 2022-03-29
- Published: 2022-10-13
- Granted: 2025-02-11
- Earliest claimed: 2021-04-08
- Assignees: Semiconductor Components Industries, LLC
- Applicants: Semiconductor Components Industries, LLC
- Inventors: Clifford Drowley; Andrew P. Edwards; Hao Cui; Subhash Srinivas Pidaparthi; Michael Craven; David DeMuynck
- Web page: https://patentgrep.com/patent/US12224344B2

## CPC

- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/831: {Vertical FETs having PN junction gate electrodes (Vertical SIT H10D30/202)}
- H10D 30/01: Manufacture or treatment
- H10D 30/0241: {doping of vertical sidewalls, e.g. using tilted or multi-angled implants}
- H10D 30/0515: {of vertical FETs having PN homojunction gates}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10P 50/693: {characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A III-N-based vertical transistor includes a III-N substrate, a source, a drain, and a channel comprising a III-N crystal material and extending between the source and the drain. The channel includes at least one sidewall surface aligned ±0.3° with respect to an m-plane of the III-N crystal material. The III-N-based vertical transistor also includes a gate electrically coupled to the at least one sidewall surface of the channel.

## Claims

### Claim 1

A method of fabricating a field effect transistor (FET) on a III-nitride substrate, the method comprising:
providing the III-nitride substrate;
aligning a mask with respect to the III-nitride substrate;
forming a mask layer including a plurality of mask patterns;
providing a plurality of gate interface regions aligned parallel to one of the <1210> directions of the III-nitride substrate ±0.3° and adjoining a channel region extending between a source region and a drain region;
forming a plurality of gate regions in contact with the plurality of gate interface regions;
forming a gate electrode coupled to the plurality of gate regions;
forming a source electrode coupled to the source region; and
forming a drain electrode coupled to the drain region.

### Claim 2 (depends on 1)

The method of claim 1 wherein aligning the mask with respect to the III-nitride substrate comprises:
determining an orientation of an alignment reference structure of the III-nitride substrate, wherein the alignment reference structure defines a reference direction on the III-nitride substrate; and
determining the <1210> directions of the III-nitride substrate.

### Claim 3 (depends on 2)

The method of claim 2 further comprising:
computing a difference between the reference direction and the <1210> directions; and
aligning a feature of one or more of the plurality of mask patterns based on the difference.

### Claim 4 (depends on 2)

The method of claim 2 further comprising:
computing a difference between the reference direction and the <1210> directions;
aligning the mask to the alignment reference structure; and
thereafter, re-aligning the mask based on the difference.

### Claim 5 (depends on 2)

The method of claim 2 wherein determining the <1210> directions of the III-nitride substrate comprises analyzing the III-nitride substrate using at least one of an x-ray diffraction technique or an optical diffraction technique.

### Claim 6 (depends on 1)

The method of claim 1 wherein each mask pattern of the plurality of mask patterns includes a feature aligned parallel to one of the <1210> directions of the III-nitride substrate ±0.3°.

### Claim 7 (depends on 1)

The method of claim 1 wherein forming the drain electrode comprises forming a back-side metal electrode on the III-nitride substrate.

### Claim 8 (depends on 1)

The method of claim 1, wherein:
forming the plurality of gate regions comprises epitaxially regrowing the plurality of gate regions.

### Claim 9

A method of fabricating a field effect transistor (FET) on a III-nitride substrate, the method comprising:
providing the III-nitride substrate comprising an alignment reference structure, wherein the alignment reference structure defines a reference direction on the III-nitride substrate;
determining <1210> directions of the III-nitride substrate;
computing a difference between the reference direction and the <1210> directions to define a correction factor;
aligning a mask with respect to the III-nitride substrate using correction factor;
forming a mask layer including a plurality of mask patterns;
providing a plurality of gate interface regions aligned parallel to one of the <1210> directions of the III-nitride substrate ±0.3° and defining a channel region extending between a source region and a drain region;
forming a plurality of gate regions in contact with the plurality of gate interface regions;
forming a gate electrode coupled to the plurality of gate regions;
forming a source electrode coupled to the source region; and
forming a drain electrode coupled to the drain region.

### Claim 10 (depends on 9)

The method of claim 9 wherein:
each mask pattern of the plurality of mask patterns includes a feature aligned parallel to one of the <1210> directions of the III-nitride substrate ±0.3°.

### Claim 11 (depends on 9)

The method of claim 9, wherein:
forming the plurality of gate regions comprises epitaxially regrowing the plurality of gate regions.

### Claim 12 (depends on 9)

The method of claim 9, wherein:
providing the plurality of gate interface regions comprises providing a fin defining the channel region vertically extending between the source region and the drain region.

### Claim 13 (depends on 9)

The method of claim 9, wherein aligning the mask comprises:
aligning the mask to the alignment reference structure; and
thereafter, re-aligning the mask based on the correction factor.

### Claim 14 (depends on 9)

The method of claim 9, wherein:
providing the III-nitride substrate comprises providing the alignment reference structure comprising an orientation flat.