# US 12,224,337 B2 · PGaN enhancement mode HEMTs with dopant diffusion spacer

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- Number: US 12,224,337 B2
- Document ID: US12224337B2
- Status: Granted
- Kind: B2
- Application number: 17/132,951
- Filed: 2020-12-23
- Published: 2022-06-23
- Granted: 2025-02-11
- Earliest claimed: 2020-12-23
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Michael Beumer; Robert Ehlert; Nicholas Minutillo; Michael Robinson; Patrick Wallace; Peter Wells
- Web page: https://patentgrep.com/patent/US12224337B2

## CPC

- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 62/343: {Gate regions of field-effect devices having PN junction gates}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

III-N e-mode high electron mobility transistors (HEMTs) including a dopant diffusion spacer between an impurity-doped III-N material layer and a III-N polarization layer of the HEMT material stack. The spacer may be a substantially undoped III-N material, such as GaN. With the diffusion spacer, P-type impurities within the pGaN are setback from the polarization layer sufficiently to avoid significant levels of P-type impurities from entering the III-N material interface where the 2DEG resides. With the diffusion spacer, clustering of impurities near the 2DEG may be avoided and a III-N e-mode HEMT may achieve higher drive currents.

## Claims

### Claim 1

A Group III-nitride (III-N) transistor, comprising:
a channel layer comprising a first III-N material;
a polarization layer over the channel layer, wherein the polarization layer is a second III-N material with more Al than the first III-N material;
a p-type layer over the polarization layer, wherein the p-type layer is a third III-N material comprising a greater concentration of a P-type impurity than either the channel layer or the polarization layer;
a spacer layer between, and in contact with, the polarization layer and the p-type layer, wherein the spacer layer is the third III-N material, but with a lower concentration of the P-type impurity than the p-type layer;
a gate terminal over the spacer layer; and
source and drain terminals coupled to the channel layer.

### Claim 2 (depends on 1)

The III-N transistor of claim 1, wherein:
the P-type impurity comprises Mg;
a concentration of Mg within the p-type layer is at least 1e19 atoms/cm3; and
the spacer layer has thickness of at least 2 nm.

### Claim 3 (depends on 2)

The III-N transistor of claim 2, wherein:
the spacer layer has a thickness of less than 10 nm; and
the p-type layer has a thickness of at least 5 nm.

### Claim 4 (depends on 1)

The III-N transistor of claim 1, wherein:
the p-type layer has thickness of 5-20 nm; and
a concentration of the P-type impurity within the spacer layer is at least an order of magnitude lower than within the p-type layer.

### Claim 5 (depends on 1)

The III-N transistor of claim 1, wherein the spacer layer and the p-type layer both comprise less Al than the polarization layer.

### Claim 6 (depends on 1)

The III-N transistor of claim 1, wherein:
the first III-N material is a binary alloy of Ga and N;
the third III-N material is a binary alloy of Ga and N;
and
the second III-N material is a ternary alloy of Al, Ga and N.

### Claim 7 (depends on 6)

The III-N transistor of claim 6, wherein:
the polarization layer has a thickness of 5-15 nm; and
the channel layer has a thickness of at least 50 nm.

### Claim 8 (depends on 1)

The III-N transistor of claim 1, wherein a concentration of the P-type impurity within the polarization layer is no more than 1e18 atoms/cm3.

### Claim 9 (depends on 8)

The III-N transistor of claim 8, wherein the P-type impurity is Mg and a concentration of Mg within the polarization layer is no more than 1e17 atoms/cm3.

### Claim 10 (depends on 1)

The III-N transistor of claim 1, further comprising a dielectric material between the p-type layer and the gate terminal.

### Claim 11

A system comprising:
a power supply; and
a radio transceiver electrically coupled to the power supply, wherein at least one of the power supply and the radio transceiver comprise a Group III-nitride (III-N) transistor, and
wherein the III-N transistor comprises:
a channel layer comprising a first Group III-nitride (III-N) material;
a polarization layer over the channel layer, wherein the polarization layer comprises a second III-N material with more Al than the first III-N material;
a p-type layer over the polarization layer, wherein the p-type layer is a binary alloy of Ga and N comprising Mg;
a spacer layer between the polarization layer and the p-type layer, wherein the spacer layer is in contact with the p-type layer and is a binary alloy of Ga and N that has a lower concentration of Mg than the p-type layer;
a gate terminal over the spacer layer; and
source and drain terminals coupled to the channel layer.

### Claim 12 (depends on 11)

The system of claim 11, wherein:
the channel layer has a thickness of at least 50 nm and consists essentially of Ga and N;
the spacer layer has a thickness of 2-10 nm and consists essentially of Ga and N;
the p-type layer has a thickness of at least 5 nm and consists essentially of Ga and N with a concentration of Mg of at least 1e19 atoms/cm3; and
the polarization layer is 5-15 nm of AlxGa1xN with a concentration of Mg no more than 1e18 atoms/cm3.

### Claim 13 (depends on 11)

The system of claim 11, further comprising a battery coupled to the power supply.

### Claim 14 (depends on 11)

The system of claim 11, wherein the radio transceiver comprises a power amplifier on a transmit path and a low noise amplifier on a receive path, at least one of which comprises the III-N transistor.

### Claim 15

An apparatus, comprising:
a transistor channel layer comprising a first III-N material;
a polarization layer over the channel layer, wherein the polarization layer comprises a second III-N material with more Al than the first III-N material;
a p-type layer over the polarization layer, wherein the p-type layer has a thickness of at least 5 nm and comprises a III-N material comprising a P-type impurity at a concentration of at least 1e19 atoms/cm3;
a spacer layer between the polarization layer and the p-type layer, wherein the spacer layer has a thickness of 2-10 nm and comprises a III-N material with a lower concentration of the P-type impurity than the p-type layer;
a transistor gate terminal over the spacer layer; and
transistor source and drain terminals coupled to the transistor channel layer.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein the spacer layer is a binary alloy of Ga and N.

### Claim 17 (depends on 16)

The apparatus of claim 16, wherein the p-type layer is a binary alloy of Ga and N.

### Claim 18 (depends on 15)

The apparatus of claim 15, wherein a concentration of the P-type impurity within the polarization layer is no more than 1e18 atoms/cm3, and wherein the concentration of the P-type impurity within the spacer layer is between the concentration of the P-type impurity within the p-type layer and the concentration of the P-type impurity within the polarization layer.

### Claim 19 (depends on 15)

The apparatus of claim 15, wherein the spacer layer is in direct contact with the p-type layer.

### Claim 20 (depends on 19)

The apparatus of claim 19, wherein the spacer layer is in direct contact with the polarization layer.