# US 12,224,335 B2 · Semiconductor device and fabrication method thereof

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- Number: US 12,224,335 B2
- Document ID: US12224335B2
- Status: Granted
- Kind: B2
- Application number: 17/867,640
- Filed: 2022-07-18
- Published: 2023-12-21
- Granted: 2025-02-11
- Earliest claimed: 2022-06-20
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Ching-Chung Yang
- Web page: https://patentgrep.com/patent/US12224335B2

## CPC

- H10D 64/01306: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 30/022: {having lightly-doped source or drain extensions selectively formed at the sides of the gates}
- H10D 30/027: {of lateral single-gate IGFETs}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10P 30/22: using masks
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a substrate of first conductivity type; a first heavily doped region and a second heavily doped region of second conductivity type spaced apart from the first heavily doped region, located in the substrate; a channel region in the substrate and between the first heavily doped region and the second heavily doped region; a gate disposed on the channel region; a hard mask layer covering a top surface and a sidewall of the gate; and a spacer disposed on a sidewall of the hard mask layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate of a first conductivity type;
a first heavily doped region of a second conductivity type in the substrate;
a second heavily doped region of the second conductivity type spaced apart from the first heavily doped region, located in the substrate;
a channel region in the substrate and between the first heavily doped region and the second heavily doped region;
a gate disposed on the channel region;
a hard mask layer covering a top surface and a sidewall of the gate, wherein the gate is a polysilicon gate, and wherein the hard mask layer is in direct contact with the polysilicon gate, wherein the hard mask layer is a bi-layer structure comprising a silicon nitride lower layer and a silicon oxide upper layer, wherein a sidewall of the silicon nitride lower layer is flush with a sidewall of the silicon oxide upper layer; and
a spacer disposed on a sidewall of the hard mask layer, wherein the spacer is in direct contact with the sidewall of the silicon nitride lower layer and the sidewall of silicon oxide upper layer.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the silicon nitride lower layer has a thickness of about 200 angstroms.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the silicon oxide upper layer has a thickness of about 700 angstroms.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the spacer comprises a silicon nitride spacer.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4, wherein the spacer further comprises a silicon oxide spacer.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1 further comprising:
a well of the first conductivity type in the substrate;
a first drift region of the second conductivity type disposed in the well, wherein the first heavily doped region is disposed in the first drift region and is in proximity to the spacer; and
a second drift region of the second conductivity type disposed in the well, wherein the second heavily doped region is disposed in the second drift region and is in proximity to the spacer.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein the first conductivity type is P type and the second conductivity type is N type.

### Claim 8

A method of fabricating a semiconductor device, comprising:
providing a substrate of a first conductivity type;
forming a first heavily doped region of a second conductivity type in the substrate;
forming a second heavily doped region of the second conductivity type spaced apart from the first heavily doped region, in the substrate;
forming a channel region in the substrate and between the first heavily doped region and the second heavily doped region;
forming a gate on the channel region;
forming a hard mask layer covering a top surface and a sidewall of the gate, wherein the gate is a polysilicon gate, and wherein the hard mask layer is in direct contact with the polysilicon gate, wherein the hard mask layer is a bi-layer structure comprising a silicon nitride lower layer and a silicon oxide upper layer, wherein a sidewall of the silicon nitride lower layer is flush with a sidewall of the silicon oxide upper layer; and
forming a spacer on a sidewall of the hard mask layer, wherein the spacer is in direct contact with the sidewall of the silicon nitride lower layer and the sidewall of silicon oxide upper layer.

### Claim 9 (depends on 8)

The method according to claim 8, wherein the silicon nitride lower layer has a thickness of about 200 angstroms.

### Claim 10 (depends on 8)

The method according to claim 8, wherein the silicon oxide upper layer has a thickness of about 700 angstroms.

### Claim 11 (depends on 8)

The method according to claim 8, wherein the spacer comprises a silicon nitride spacer.

### Claim 12 (depends on 11)

The method according to claim 11, wherein the spacer further comprises a silicon oxide spacer.

### Claim 13 (depends on 8)

The method according to claim 8 further comprising:
forming a well of the first conductivity type in the substrate;
forming a first drift region of the second conductivity type in the well, wherein the first heavily doped region is disposed in the first drift region and is in proximity to the spacer; and
forming a second drift region of the second conductivity type disposed in the well, wherein the second heavily doped region is disposed in the second drift region and is in proximity to the spacer.

### Claim 14 (depends on 8)

The method according to claim 8, wherein the first conductivity type is P type and the second conductivity type is N type.