# US 12,224,334 B2 · Semiconductor device with gate dielectric formed using selective deposition

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- Number: US 12,224,334 B2
- Document ID: US12224334B2
- Status: Granted
- Kind: B2
- Application number: 18/324,636
- Filed: 2023-05-26
- Published: 2023-10-05
- Granted: 2025-02-11
- Earliest claimed: 2020-04-09
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.; National Taiwan University; National Taiwan Normal University
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.; National Taiwan University; National Taiwan Normal University
- Inventors: Tung-Ying Lee; Tse-An Chen; Tzu-Chung Wang; Miin-Jang Chen; Yu-Tung Yin; Meng-Chien Yang
- Web page: https://patentgrep.com/patent/US12224334B2

## CPC

- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 30/0194: {the stacked channels having different properties}
- H10D 30/0197: {the inner spacers having different properties}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/504: {wherein the stacked channels have different properties}
- H10D 30/507: {characterised by inner spacers between adjacent channels}
- H10D 30/508: {characterised by the relative sizes, shapes or dispositions of the inner spacers}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/01334: {by defining the insulator using a sidewall spacer mask, a transformation under a mask or a plating at a sidewall}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/679: {comprising air gaps}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10P 14/3462: {Nanowires}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3454: {Amorphous}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a plurality of semiconductor layers arranged one above another, and source/drain epitaxial regions on opposite sides of the plurality of semiconductor layers. The semiconductor device further includes a gate structure surrounding each of the plurality of semiconductor layers. The gate structure includes interfacial layers respectively over the plurality of semiconductor layers, a high-k dielectric layer over the interfacial layers, and a gate metal over the high-k dielectric layer. The gate structure further includes gate spacers spacing apart the gate structure from the source/drain epitaxial regions. A top position of the high-k dielectric layer is lower than top positions of the gate spacers.

## Claims

### Claim 1

A semiconductor device, comprising:
a plurality of semiconductor layers arranged one above another;
source/drain epitaxial regions on opposite sides of the plurality of semiconductor layers;
a gate structure surrounding each of the plurality of semiconductor layers, the gate structure comprising interfacial layers respectively over the plurality of semiconductor layers, a high-k dielectric layer over the interfacial layers, and a gate metal over the high-k dielectric layer; and
gate spacers spacing apart the gate structure from the source/drain epitaxial regions, wherein a top position of the high-k dielectric layer is lower than top positions of the gate spacers, and the high-k dielectric layer is spaced apart from one of the gate spacers by a void region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the top position of the high-k dielectric layer is lower than a top position of the gate metal.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein end surfaces of the high-k dielectric layer are respectively aligned with end surfaces of the interfacial layers.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising:
a self-assembled-monolayer below a topmost one of the plurality of semiconductor layers.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the self-assembled-monolayer is in contact with a sidewall of the gate structure.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the high-k dielectric layer continuously extends from a bottommost one of the plurality of semiconductor layers to a topmost one of the plurality of semiconductor layers.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the gate structure comprises a plurality of the high-k dielectric layers respectively over the plurality of semiconductor layers, and the high-k dielectric layers are spaced apart from each other.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the gate metal is in contact with the gate spacers.

### Claim 9

A semiconductor device, comprising:
source/drain epitaxial structures over a substrate;
a plurality of channel layers extending between the source/drain epitaxial structures;
a gate structure wrapping around the plurality of channel layers, the gate structure comprising a high-k dielectric layer and a gate metal over the high-k dielectric layer;
a first gate spacer between the gate structure and a first one of the source/drain epitaxial structures; and
a second gate spacer between the gate structure and a second one of the source/drain epitaxial structures,
wherein the high-k dielectric layer is spaced apart from the first gate spacer.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the gate metal interposes the high-k dielectric layer and the first gate spacer.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein the high-k dielectric layer is spaced apart from the second gate spacer.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the gate metal interposes the high-k dielectric layer and the second gate spacer.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein the high-k dielectric layer is spaced apart from the first gate spacer by a void.

### Claim 14 (depends on 9)

The semiconductor device of claim 9, wherein the gate metal is in contact with end surfaces of the high-k dielectric layer.

### Claim 15

A semiconductor device, comprising:
a source region and a drain region spaced apart in a first direction over a substrate;
a plurality of channel regions extending between the source region and the drain region;
a high-k dielectric layer over the plurality of channel regions, wherein in a cross section taken along a second direction perpendicular to the first direction, the high-k dielectric layer continuously extending from below a bottommost one of the channel regions to above a topmost one of the channel regions;
a gate metal over the high-k dielectric layer, wherein in a cross section taken along the first direction, the gate metal has a top surface higher than a top surface of the high-k dielectric layer; and
gate spacers interfacing opposite sidewalls of the gate metal, wherein the gate spacers are separated from the high-k dielectric layer by void regions.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the gate spacers are separated from the high-k dielectric layer at least further by the gate metal.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein in the cross section taken along the first direction, the gate metal wraps around three sides of the high-k dielectric layer.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, wherein in the cross section taken along the first direction, the high-k dielectric layer resembles a linear pattern.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, further comprising:
a self-assembled-monolayer in contact with the plurality of channel regions.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein the top surface of the high-k dielectric layer is higher than a top surface of the self-assembled-monolayer.